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Published: Apr 28, 2022 License: MIT Imports: 6 Imported by: 0



The Arm architecture is a Reduced Instruction Set Computer (RISC) architecture with the following RISC architecture features:

* A large uniform register file.

  • A load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents.
  • Simple addressing modes, with all load/store addresses determined from register contents and instruction fields only.

AArch64 is the 64-bit Execution state, meaning addresses are held in 64-bit registers, and instructions in the base instruction set can use 64-bit registers for their processing.



This section is empty.


View Source
var (
	OP_Xd    = OpcodeChunk{OT_Register64, 5, 0}
	OP_Xn    = OpcodeChunk{OT_Register64, 5, 0}
	OP_Xm    = OpcodeChunk{OT_Register64, 5, 0}
	OP_Wd    = OpcodeChunk{OT_Register32, 5, 0}
	OP_Wn    = OpcodeChunk{OT_Register32, 5, 0}
	OP_Wm    = OpcodeChunk{OT_Register32, 5, 0}
	OP_Imm12 = OpcodeChunk{OT_ImmediateValue, 12, 0}
	OP_Imm16 = OpcodeChunk{OT_ImmediateValue, 16, 0}
View Source
var Registers32 []*Register = []*Register{
	W0, W1, W2, W3, W4, W5, W6, W7, W8,
	W9, W10, W11, W12, W13, W14, W15, W16,
	W17, W18, W19, W20, W21, W22, W23, W24,
	W25, W26, W27, W28, W29, W30,
View Source
var Registers64 []*Register = []*Register{
	X0, X1, X2, X3, X4, X5, X6, X7, X8,
	X9, X10, X11, X12, X13, X14, X15, X16,
	X17, X18, X19, X20, X21, X22, X23, X24,
	X25, X26, X27, X28, X29, X30,


This section is empty.


type Condition

type Condition uint8
const (
	// Integer: equal; Float: equal; Condition: Z==1
	EQ Condition = 0b0000
	// Integer: not equal; Float: not equal or unordered; Condition: Z==0
	NE Condition = 0b0001
	// Integer: carry set; Float: greater than, equal or unordered; Condition: C==1
	CS_or_HS Condition = 0b0010
	// Integer: carry clear; Float: less than; Condition: C==0
	CC_or_LO Condition = 0b0011
	// Integer: minus, negative; Float: less than; Condition: N==1
	MI Condition = 0b0100
	// Integer: plus, positive or zero; Float: greater than, equal, unordered; Condition: N==0
	PL Condition = 0b0101
	// Integer: overflow; Float: unordered; Condition: V==1
	VS Condition = 0b0110
	// Integer: no overflow; Float: ordered; Condition: V==0
	VC Condition = 0b0111
	// Integer: unsigned higher; Float: greater than, unordered; Condition: C==1 && Z == 0
	HI Condition = 0b1000
	// Integer: unsigned lower or same; Float: less than or equal; Condition: !(C==1 && Z == 0)
	LS Condition = 0b1001
	// Integer: signed greater than or equal; Float: greater than or equal; Condition: N == V
	GE Condition = 0b1010
	// Integer: signed less than; Float: less than or unordered; Condition: N != V
	LT Condition = 0b1011
	// Integer: signed greater than; Float: greater than; Condition: Z==0 && N==V
	GT Condition = 0b1100
	// Integer: signed less than or equal; Float: less than, equal, unordered; Condition: !(Z==0 && N==V)
	LE Condition = 0b1101
	// Always
	AL Condition = 0b1110

type GroupType

type GroupType uint8
const (
	GT_Reserved        GroupType = 0b0000
	GT_Unallocated1    GroupType = 0b0001
	GT_SVE             GroupType = 0b0010
	GT_Unallocated2    GroupType = 0b0011
	GT_Data_Immediate1 GroupType = 0b1000
	GT_Data_Immediate2 GroupType = 0b1001
	GT_Load_Store1     GroupType = 0b0100
	GT_Load_Store2     GroupType = 0b0110
	GT_Load_Store3     GroupType = 0b1100
	GT_Load_Store4     GroupType = 0b1110
	GT_Data1           GroupType = 0b0101
	GT_Data2           GroupType = 0b1101
	GT_Data_Scalar1    GroupType = 0b0111
	GT_Data_Scalar2    GroupType = 0b1111

type InstructionFormat

type InstructionFormat struct {
	LeadingBits uint8 // 3 bits
	Op0         uint8 // 4 bits
	Data        uint8 // Remainging 25 bits

func (*InstructionFormat) Encode

func (i *InstructionFormat) Encode() lib.MachineCode

type Int32

type Int32 int32

func (Int32) Encode

func (i Int32) Encode() []uint8

func (Int32) String

func (i Int32) String() string

func (Int32) Type

func (i Int32) Type() lib.Type

func (Int32) Width

func (t Int32) Width() lib.Size

type Opcode

type Opcode struct {
	Name     string
	Operands []OpcodeChunk

func (*Opcode) Encode

func (o *Opcode) Encode(ops []lib.Operand) ([]uint8, error)

func (*Opcode) GetOperands

func (o *Opcode) GetOperands() []OperandType

func (*Opcode) MatchesOperands

func (o *Opcode) MatchesOperands(operands []lib.Operand) bool

func (*Opcode) String

func (o *Opcode) String() string

type OpcodeChunk

type OpcodeChunk struct {
	Size  uint8 // Size of encoding in bits
	Value uint64

func OP_Exact

func OP_Exact(size uint8, value uint64, description ...string) OpcodeChunk

type OperandType

type OperandType int
const (
	OT_Exact          OperandType = iota
	OT_Register32     OperandType = iota
	OT_Register64     OperandType = iota
	OT_ImmediateValue OperandType = iota

func (OperandType) String

func (i OperandType) String() string

type Register

type Register struct {
	Name     string
	Register uint8
	Size     Size
var (
	X0  *Register = NewRegister("x0", 0, QUADWORD)
	X1  *Register = NewRegister("x1", 1, QUADWORD)
	X2  *Register = NewRegister("x2", 2, QUADWORD)
	X3  *Register = NewRegister("x3", 3, QUADWORD)
	X4  *Register = NewRegister("x4", 4, QUADWORD)
	X5  *Register = NewRegister("x5", 5, QUADWORD)
	X6  *Register = NewRegister("x6", 6, QUADWORD)
	X7  *Register = NewRegister("x7", 7, QUADWORD)
	X8  *Register = NewRegister("x8", 8, QUADWORD)
	X9  *Register = NewRegister("x9", 9, QUADWORD)
	X10 *Register = NewRegister("x10", 10, QUADWORD)
	X11 *Register = NewRegister("x11", 11, QUADWORD)
	X12 *Register = NewRegister("x12", 12, QUADWORD)
	X13 *Register = NewRegister("x13", 13, QUADWORD)
	X14 *Register = NewRegister("x14", 14, QUADWORD)
	X15 *Register = NewRegister("x15", 15, QUADWORD)
	X16 *Register = NewRegister("x16", 16, QUADWORD)
	X17 *Register = NewRegister("x17", 17, QUADWORD)
	X18 *Register = NewRegister("x18", 18, QUADWORD)
	X19 *Register = NewRegister("x19", 19, QUADWORD)
	X20 *Register = NewRegister("x20", 20, QUADWORD)
	X21 *Register = NewRegister("x21", 21, QUADWORD)
	X22 *Register = NewRegister("x22", 22, QUADWORD)
	X23 *Register = NewRegister("x23", 23, QUADWORD)
	X24 *Register = NewRegister("x24", 24, QUADWORD)
	X25 *Register = NewRegister("x25", 25, QUADWORD)
	X26 *Register = NewRegister("x26", 26, QUADWORD)
	X27 *Register = NewRegister("x27", 27, QUADWORD)
	X28 *Register = NewRegister("x28", 28, QUADWORD)
	X29 *Register = NewRegister("x29", 29, QUADWORD)
	X30 *Register = NewRegister("x30", 30, QUADWORD)

	SP  *Register = NewRegister("sp", 31, QUADWORD) // stack pointer. MUST BE 16 byte aligned when accessing memory
	XZR *Register = NewRegister("zr", 31, QUADWORD) // zero register

	W0  *Register = NewRegister("w0", 0, DOUBLE)
	W1  *Register = NewRegister("w1", 1, DOUBLE)
	W2  *Register = NewRegister("w2", 2, DOUBLE)
	W3  *Register = NewRegister("w3", 3, DOUBLE)
	W4  *Register = NewRegister("w4", 4, DOUBLE)
	W5  *Register = NewRegister("w5", 5, DOUBLE)
	W6  *Register = NewRegister("w6", 6, DOUBLE)
	W7  *Register = NewRegister("w7", 7, DOUBLE)
	W8  *Register = NewRegister("w8", 8, DOUBLE)
	W9  *Register = NewRegister("w9", 9, DOUBLE)
	W10 *Register = NewRegister("w10", 10, DOUBLE)
	W11 *Register = NewRegister("w11", 11, DOUBLE)
	W12 *Register = NewRegister("w12", 12, DOUBLE)
	W13 *Register = NewRegister("w13", 13, DOUBLE)
	W14 *Register = NewRegister("w14", 14, DOUBLE)
	W15 *Register = NewRegister("w15", 15, DOUBLE)
	W16 *Register = NewRegister("w16", 16, DOUBLE)
	W17 *Register = NewRegister("w17", 17, DOUBLE)
	W18 *Register = NewRegister("w18", 18, DOUBLE)
	W19 *Register = NewRegister("w19", 19, DOUBLE)
	W20 *Register = NewRegister("w20", 20, DOUBLE)
	W21 *Register = NewRegister("w21", 21, DOUBLE)
	W22 *Register = NewRegister("w22", 22, DOUBLE)
	W23 *Register = NewRegister("w23", 23, DOUBLE)
	W24 *Register = NewRegister("w24", 24, DOUBLE)
	W25 *Register = NewRegister("w25", 25, DOUBLE)
	W26 *Register = NewRegister("w26", 26, DOUBLE)
	W27 *Register = NewRegister("w27", 27, DOUBLE)
	W28 *Register = NewRegister("w28", 28, DOUBLE)
	W29 *Register = NewRegister("w29", 29, DOUBLE)
	W30 *Register = NewRegister("w30", 30, DOUBLE)
	WSP *Register = NewRegister("wsp", 31, DOUBLE) // current stack pointer
	WZR *Register = NewRegister("wzr", 31, DOUBLE) // zero register


func Get64BitRegisterByIndex

func Get64BitRegisterByIndex(ix uint8) *Register

func GetFloatingPointRegisterByIndex

func GetFloatingPointRegisterByIndex(ix uint8) *Register


func NewRegister

func NewRegister(name string, register uint8, size Size) *Register

func (*Register) Encode

func (r *Register) Encode() uint8

func (*Register) ForOperandWidth

func (r *Register) ForOperandWidth(w Size) *Register

func (*Register) Get32BitRegister

func (r *Register) Get32BitRegister() *Register

func (*Register) String

func (r *Register) String() string

func (*Register) Type

func (r *Register) Type() Type

func (*Register) Width

func (r *Register) Width() Size

type Uint16

type Uint16 uint16

func (Uint16) Encode

func (i Uint16) Encode() []uint8

func (Uint16) String

func (i Uint16) String() string

func (Uint16) Type

func (i Uint16) Type() lib.Type

func (Uint16) Width

func (t Uint16) Width() lib.Size

type Uint32

type Uint32 uint32

func (Uint32) Encode

func (i Uint32) Encode() []uint8

func (Uint32) String

func (i Uint32) String() string

func (Uint32) Type

func (i Uint32) Type() lib.Type

func (Uint32) Width

func (t Uint32) Width() lib.Size

type Uint64

type Uint64 uint64

func (Uint64) Encode

func (i Uint64) Encode() []uint8

func (Uint64) String

func (i Uint64) String() string

func (Uint64) Type

func (i Uint64) Type() lib.Type

func (Uint64) Width

func (t Uint64) Width() lib.Size

type Uint8

type Uint8 uint8

func (Uint8) Encode

func (i Uint8) Encode() []uint8

func (Uint8) String

func (i Uint8) String() string

func (Uint8) Type

func (i Uint8) Type() lib.Type

func (Uint8) Width

func (t Uint8) Width() lib.Size

type Value

type Value interface {
	Type() lib.Type
	String() string
	Encode() []uint8
	Width() lib.Size

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