x86

package
Version: v0.0.0-...-984e81f Latest Latest
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Published: Jan 20, 2018 License: BSD-3-Clause Imports: 8 Imported by: 0

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Index

Constants

View Source
const (
	REG_AL = obj.RBaseAMD64 + iota
	REG_CL
	REG_DL
	REG_BL
	REG_SPB
	REG_BPB
	REG_SIB
	REG_DIB
	REG_R8B
	REG_R9B
	REG_R10B
	REG_R11B
	REG_R12B
	REG_R13B
	REG_R14B
	REG_R15B

	REG_AX
	REG_CX
	REG_DX
	REG_BX
	REG_SP
	REG_BP
	REG_SI
	REG_DI
	REG_R8
	REG_R9
	REG_R10
	REG_R11
	REG_R12
	REG_R13
	REG_R14
	REG_R15

	REG_AH
	REG_CH
	REG_DH
	REG_BH

	REG_F0
	REG_F1
	REG_F2
	REG_F3
	REG_F4
	REG_F5
	REG_F6
	REG_F7

	REG_M0
	REG_M1
	REG_M2
	REG_M3
	REG_M4
	REG_M5
	REG_M6
	REG_M7

	REG_X0
	REG_X1
	REG_X2
	REG_X3
	REG_X4
	REG_X5
	REG_X6
	REG_X7
	REG_X8
	REG_X9
	REG_X10
	REG_X11
	REG_X12
	REG_X13
	REG_X14
	REG_X15

	REG_Y0
	REG_Y1
	REG_Y2
	REG_Y3
	REG_Y4
	REG_Y5
	REG_Y6
	REG_Y7
	REG_Y8
	REG_Y9
	REG_Y10
	REG_Y11
	REG_Y12
	REG_Y13
	REG_Y14
	REG_Y15

	REG_CS
	REG_SS
	REG_DS
	REG_ES
	REG_FS
	REG_GS

	REG_GDTR /* global descriptor table register */
	REG_IDTR /* interrupt descriptor table register */
	REG_LDTR /* local descriptor table register */
	REG_MSW  /* machine status word */
	REG_TASK /* task register */

	REG_CR0
	REG_CR1
	REG_CR2
	REG_CR3
	REG_CR4
	REG_CR5
	REG_CR6
	REG_CR7
	REG_CR8
	REG_CR9
	REG_CR10
	REG_CR11
	REG_CR12
	REG_CR13
	REG_CR14
	REG_CR15

	REG_DR0
	REG_DR1
	REG_DR2
	REG_DR3
	REG_DR4
	REG_DR5
	REG_DR6
	REG_DR7

	REG_TR0
	REG_TR1
	REG_TR2
	REG_TR3
	REG_TR4
	REG_TR5
	REG_TR6
	REG_TR7

	REG_TLS

	MAXREG

	REG_CR = REG_CR0
	REG_DR = REG_DR0
	REG_TR = REG_TR0

	REGARG   = -1
	REGRET   = REG_AX
	FREGRET  = REG_X0
	REGSP    = REG_SP
	REGCTXT  = REG_DX
	REGEXT   = REG_R15     /* compiler allocates external registers R15 down */
	FREGMIN  = REG_X0 + 5  /* first register variable */
	FREGEXT  = REG_X0 + 15 /* first external register */
	T_TYPE   = 1 << 0
	T_INDEX  = 1 << 1
	T_OFFSET = 1 << 2
	T_FCONST = 1 << 3
	T_SYM    = 1 << 4
	T_SCONST = 1 << 5
	T_64     = 1 << 6
	T_GOTYPE = 1 << 7
)
View Source
const (
	AAAA = obj.ABaseAMD64 + obj.A_ARCHSPECIFIC + iota
	AAAD
	AAAM
	AAAS
	AADCB
	AADCL
	AADCQ
	AADCW
	AADCXL
	AADCXQ
	AADDB
	AADDL
	AADDPD
	AADDPS
	AADDQ
	AADDSD
	AADDSS
	AADDSUBPD
	AADDSUBPS
	AADDW
	AADJSP
	AADOXL
	AADOXQ
	AAESDEC
	AAESDECLAST
	AAESENC
	AAESENCLAST
	AAESIMC
	AAESKEYGENASSIST
	AANDB
	AANDL
	AANDNL
	AANDNPD
	AANDNPS
	AANDNQ
	AANDPD
	AANDPS
	AANDQ
	AANDW
	AARPL
	ABEXTRL
	ABEXTRQ
	ABLENDPD
	ABLENDPS
	ABLSIL
	ABLSIQ
	ABLSMSKL
	ABLSMSKQ
	ABLSRL
	ABLSRQ
	ABOUNDL
	ABOUNDW
	ABSFL
	ABSFQ
	ABSFW
	ABSRL
	ABSRQ
	ABSRW
	ABSWAPL
	ABSWAPQ
	ABTCL
	ABTCQ
	ABTCW
	ABTL
	ABTQ
	ABTRL
	ABTRQ
	ABTRW
	ABTSL
	ABTSQ
	ABTSW
	ABTW
	ABYTE
	ABZHIL
	ABZHIQ
	ACDQ
	ACLC
	ACLD
	ACLFLUSH
	ACLI
	ACLTS
	ACMC
	ACMOVLCC
	ACMOVLCS
	ACMOVLEQ
	ACMOVLGE
	ACMOVLGT
	ACMOVLHI
	ACMOVLLE
	ACMOVLLS
	ACMOVLLT
	ACMOVLMI
	ACMOVLNE
	ACMOVLOC
	ACMOVLOS
	ACMOVLPC
	ACMOVLPL
	ACMOVLPS
	ACMOVQCC
	ACMOVQCS
	ACMOVQEQ
	ACMOVQGE
	ACMOVQGT
	ACMOVQHI
	ACMOVQLE
	ACMOVQLS
	ACMOVQLT
	ACMOVQMI
	ACMOVQNE
	ACMOVQOC
	ACMOVQOS
	ACMOVQPC
	ACMOVQPL
	ACMOVQPS
	ACMOVWCC
	ACMOVWCS
	ACMOVWEQ
	ACMOVWGE
	ACMOVWGT
	ACMOVWHI
	ACMOVWLE
	ACMOVWLS
	ACMOVWLT
	ACMOVWMI
	ACMOVWNE
	ACMOVWOC
	ACMOVWOS
	ACMOVWPC
	ACMOVWPL
	ACMOVWPS
	ACMPB
	ACMPL
	ACMPPD
	ACMPPS
	ACMPQ
	ACMPSB
	ACMPSD
	ACMPSL
	ACMPSQ
	ACMPSS
	ACMPSW
	ACMPW
	ACMPXCHG8B
	ACMPXCHGB
	ACMPXCHGL
	ACMPXCHGQ
	ACMPXCHGW
	ACOMISD
	ACOMISS
	ACPUID
	ACQO
	ACRC32B
	ACRC32Q
	ACVTPD2PL
	ACVTPD2PS
	ACVTPL2PD
	ACVTPL2PS
	ACVTPS2PD
	ACVTPS2PL
	ACVTSD2SL
	ACVTSD2SQ
	ACVTSD2SS
	ACVTSL2SD
	ACVTSL2SS
	ACVTSQ2SD
	ACVTSQ2SS
	ACVTSS2SD
	ACVTSS2SL
	ACVTSS2SQ
	ACVTTPD2PL
	ACVTTPS2PL
	ACVTTSD2SL
	ACVTTSD2SQ
	ACVTTSS2SL
	ACVTTSS2SQ
	ACWD
	ADAA
	ADAS
	ADECB
	ADECL
	ADECQ
	ADECW
	ADIVB
	ADIVL
	ADIVPD
	ADIVPS
	ADIVQ
	ADIVSD
	ADIVSS
	ADIVW
	ADPPD
	ADPPS
	AEMMS
	AENTER
	AEXTRACTPS
	AF2XM1
	AFABS
	AFADDD
	AFADDDP
	AFADDF
	AFADDL
	AFADDW
	AFCHS
	AFCLEX
	AFCMOVCC
	AFCMOVCS
	AFCMOVEQ
	AFCMOVHI
	AFCMOVLS
	AFCMOVNE
	AFCMOVNU
	AFCMOVUN
	AFCOMD
	AFCOMDP
	AFCOMDPP
	AFCOMF
	AFCOMFP
	AFCOMI
	AFCOMIP
	AFCOML
	AFCOMLP
	AFCOMW
	AFCOMWP
	AFCOS
	AFDECSTP
	AFDIVD
	AFDIVDP
	AFDIVF
	AFDIVL
	AFDIVRD
	AFDIVRDP
	AFDIVRF
	AFDIVRL
	AFDIVRW
	AFDIVW
	AFFREE
	AFINCSTP
	AFINIT
	AFLD1
	AFLDCW
	AFLDENV
	AFLDL2E
	AFLDL2T
	AFLDLG2
	AFLDLN2
	AFLDPI
	AFLDZ
	AFMOVB
	AFMOVBP
	AFMOVD
	AFMOVDP
	AFMOVF
	AFMOVFP
	AFMOVL
	AFMOVLP
	AFMOVV
	AFMOVVP
	AFMOVW
	AFMOVWP
	AFMOVX
	AFMOVXP
	AFMULD
	AFMULDP
	AFMULF
	AFMULL
	AFMULW
	AFNOP
	AFPATAN
	AFPREM
	AFPREM1
	AFPTAN
	AFRNDINT
	AFRSTOR
	AFSAVE
	AFSCALE
	AFSIN
	AFSINCOS
	AFSQRT
	AFSTCW
	AFSTENV
	AFSTSW
	AFSUBD
	AFSUBDP
	AFSUBF
	AFSUBL
	AFSUBRD
	AFSUBRDP
	AFSUBRF
	AFSUBRL
	AFSUBRW
	AFSUBW
	AFTST
	AFUCOM
	AFUCOMI
	AFUCOMIP
	AFUCOMP
	AFUCOMPP
	AFXAM
	AFXCHD
	AFXRSTOR
	AFXRSTOR64
	AFXSAVE
	AFXSAVE64
	AFXTRACT
	AFYL2X
	AFYL2XP1
	AHADDPD
	AHADDPS
	AHLT
	AHSUBPD
	AHSUBPS
	AIDIVB
	AIDIVL
	AIDIVQ
	AIDIVW
	AIMUL3Q
	AIMULB
	AIMULL
	AIMULQ
	AIMULW
	AINB
	AINCB
	AINCL
	AINCQ
	AINCW
	AINL
	AINSB
	AINSERTPS
	AINSL
	AINSW
	AINT
	AINTO
	AINVD
	AINVLPG
	AINW
	AIRETL
	AIRETQ
	AIRETW
	AJCC // >= unsigned
	AJCS // < unsigned
	AJCXZL
	AJCXZQ
	AJCXZW
	AJEQ // == (zero)
	AJGE // >= signed
	AJGT // > signed
	AJHI // > unsigned
	AJLE // <= signed
	AJLS // <= unsigned
	AJLT // < signed
	AJMI // sign bit set (negative)
	AJNE // != (nonzero)
	AJOC // overflow clear
	AJOS // overflow set
	AJPC // parity clear
	AJPL // sign bit clear (positive)
	AJPS // parity set
	ALAHF
	ALARL
	ALARW
	ALDDQU
	ALDMXCSR
	ALEAL
	ALEAQ
	ALEAVEL
	ALEAVEQ
	ALEAVEW
	ALEAW
	ALFENCE
	ALOCK
	ALODSB
	ALODSL
	ALODSQ
	ALODSW
	ALONG
	ALOOP
	ALOOPEQ
	ALOOPNE
	ALSLL
	ALSLW
	AMASKMOVOU
	AMASKMOVQ
	AMAXPD
	AMAXPS
	AMAXSD
	AMAXSS
	AMFENCE
	AMINPD
	AMINPS
	AMINSD
	AMINSS
	AMOVAPD
	AMOVAPS
	AMOVB
	AMOVBLSX
	AMOVBLZX
	AMOVBQSX
	AMOVBQZX
	AMOVBWSX
	AMOVBWZX
	AMOVDDUP
	AMOVHLPS
	AMOVHPD
	AMOVHPS
	AMOVL
	AMOVLHPS
	AMOVLPD
	AMOVLPS
	AMOVLQSX
	AMOVLQZX
	AMOVMSKPD
	AMOVMSKPS
	AMOVNTDQA
	AMOVNTIL
	AMOVNTIQ
	AMOVNTO
	AMOVNTPD
	AMOVNTPS
	AMOVNTQ
	AMOVO
	AMOVOU
	AMOVQ
	AMOVQL
	AMOVQOZX
	AMOVSB
	AMOVSD
	AMOVSHDUP
	AMOVSL
	AMOVSLDUP
	AMOVSQ
	AMOVSS
	AMOVSW
	AMOVUPD
	AMOVUPS
	AMOVW
	AMOVWLSX
	AMOVWLZX
	AMOVWQSX
	AMOVWQZX
	AMPSADBW
	AMULB
	AMULL
	AMULPD
	AMULPS
	AMULQ
	AMULSD
	AMULSS
	AMULW
	AMULXL
	AMULXQ
	ANEGB
	ANEGL
	ANEGQ
	ANEGW
	ANOTB
	ANOTL
	ANOTQ
	ANOTW
	AORB
	AORL
	AORPD
	AORPS
	AORQ
	AORW
	AOUTB
	AOUTL
	AOUTSB
	AOUTSL
	AOUTSW
	AOUTW
	APABSB
	APABSD
	APABSW
	APACKSSLW
	APACKSSWB
	APACKUSDW
	APACKUSWB
	APADDB
	APADDL
	APADDQ
	APADDSB
	APADDSW
	APADDUSB
	APADDUSW
	APADDW
	APALIGNR
	APAND
	APANDN
	APAUSE
	APAVGB
	APAVGW
	APBLENDW
	APCLMULQDQ
	APCMPEQB
	APCMPEQL
	APCMPEQQ
	APCMPEQW
	APCMPESTRI
	APCMPESTRM
	APCMPGTB
	APCMPGTL
	APCMPGTQ
	APCMPGTW
	APCMPISTRI
	APCMPISTRM
	APDEPL
	APDEPQ
	APEXTL
	APEXTQ
	APEXTRB
	APEXTRD
	APEXTRQ
	APEXTRW
	APHADDD
	APHADDSW
	APHADDW
	APHMINPOSUW
	APHSUBD
	APHSUBSW
	APHSUBW
	APINSRB
	APINSRD
	APINSRQ
	APINSRW
	APMADDUBSW
	APMADDWL
	APMAXSB
	APMAXSD
	APMAXSW
	APMAXUB
	APMAXUD
	APMAXUW
	APMINSB
	APMINSD
	APMINSW
	APMINUB
	APMINUD
	APMINUW
	APMOVMSKB
	APMOVSXBD
	APMOVSXBQ
	APMOVSXBW
	APMOVSXDQ
	APMOVSXWD
	APMOVSXWQ
	APMOVZXBD
	APMOVZXBQ
	APMOVZXBW
	APMOVZXDQ
	APMOVZXWD
	APMOVZXWQ
	APMULDQ
	APMULHRSW
	APMULHUW
	APMULHW
	APMULLD
	APMULLW
	APMULULQ
	APOPAL
	APOPAW
	APOPCNTL
	APOPCNTQ
	APOPCNTW
	APOPFL
	APOPFQ
	APOPFW
	APOPL
	APOPQ
	APOPW
	APOR
	APREFETCHNTA
	APREFETCHT0
	APREFETCHT1
	APREFETCHT2
	APSADBW
	APSHUFB
	APSHUFD
	APSHUFHW
	APSHUFL
	APSHUFLW
	APSHUFW
	APSIGNB
	APSIGND
	APSIGNW
	APSLLL
	APSLLO
	APSLLQ
	APSLLW
	APSRAL
	APSRAW
	APSRLL
	APSRLO
	APSRLQ
	APSRLW
	APSUBB
	APSUBL
	APSUBQ
	APSUBSB
	APSUBSW
	APSUBUSB
	APSUBUSW
	APSUBW
	APTEST
	APUNPCKHBW
	APUNPCKHLQ
	APUNPCKHQDQ
	APUNPCKHWL
	APUNPCKLBW
	APUNPCKLLQ
	APUNPCKLQDQ
	APUNPCKLWL
	APUSHAL
	APUSHAW
	APUSHFL
	APUSHFQ
	APUSHFW
	APUSHL
	APUSHQ
	APUSHW
	APXOR
	AQUAD
	ARCLB
	ARCLL
	ARCLQ
	ARCLW
	ARCPPS
	ARCPSS
	ARCRB
	ARCRL
	ARCRQ
	ARCRW
	ARDMSR
	ARDPMC
	ARDTSC
	AREP
	AREPN
	ARETFL
	ARETFQ
	ARETFW
	AROLB
	AROLL
	AROLQ
	AROLW
	ARORB
	ARORL
	ARORQ
	ARORW
	ARORXL
	ARORXQ
	AROUNDPD
	AROUNDPS
	AROUNDSD
	AROUNDSS
	ARSM
	ARSQRTPS
	ARSQRTSS
	ASAHF
	ASALB
	ASALL
	ASALQ
	ASALW
	ASARB
	ASARL
	ASARQ
	ASARW
	ASARXL
	ASARXQ
	ASBBB
	ASBBL
	ASBBQ
	ASBBW
	ASCASB
	ASCASL
	ASCASQ
	ASCASW
	ASETCC
	ASETCS
	ASETEQ
	ASETGE
	ASETGT
	ASETHI
	ASETLE
	ASETLS
	ASETLT
	ASETMI
	ASETNE
	ASETOC
	ASETOS
	ASETPC
	ASETPL
	ASETPS
	ASFENCE
	ASHLB
	ASHLL
	ASHLQ
	ASHLW
	ASHLXL
	ASHLXQ
	ASHRB
	ASHRL
	ASHRQ
	ASHRW
	ASHRXL
	ASHRXQ
	ASHUFPD
	ASHUFPS
	ASQRTPD
	ASQRTPS
	ASQRTSD
	ASQRTSS
	ASTC
	ASTD
	ASTI
	ASTMXCSR
	ASTOSB
	ASTOSL
	ASTOSQ
	ASTOSW
	ASUBB
	ASUBL
	ASUBPD
	ASUBPS
	ASUBQ
	ASUBSD
	ASUBSS
	ASUBW
	ASWAPGS
	ASYSCALL
	ASYSRET
	ATESTB
	ATESTL
	ATESTQ
	ATESTW
	AUCOMISD
	AUCOMISS
	AUNPCKHPD
	AUNPCKHPS
	AUNPCKLPD
	AUNPCKLPS
	AVADDPD
	AVADDPS
	AVADDSD
	AVADDSS
	AVADDSUBPD
	AVADDSUBPS
	AVAESDEC
	AVAESDECLAST
	AVAESENC
	AVAESENCLAST
	AVAESIMC
	AVAESKEYGENASSIST
	AVANDNPD
	AVANDNPS
	AVANDPD
	AVANDPS
	AVBLENDPD
	AVBLENDPS
	AVBLENDVPD
	AVBLENDVPS
	AVBROADCASTF128
	AVBROADCASTI128
	AVBROADCASTSD
	AVBROADCASTSS
	AVCMPPD
	AVCMPPS
	AVCMPSD
	AVCMPSS
	AVCOMISD
	AVCOMISS
	AVCVTDQ2PD
	AVCVTDQ2PS
	AVCVTPD2DQX
	AVCVTPD2DQY
	AVCVTPD2PSX
	AVCVTPD2PSY
	AVCVTPH2PS
	AVCVTPS2DQ
	AVCVTPS2PD
	AVCVTPS2PH
	AVCVTSD2SI
	AVCVTSD2SIQ
	AVCVTSD2SS
	AVCVTSI2SDL
	AVCVTSI2SDQ
	AVCVTSI2SSL
	AVCVTSI2SSQ
	AVCVTSS2SD
	AVCVTSS2SI
	AVCVTSS2SIQ
	AVCVTTPD2DQX
	AVCVTTPD2DQY
	AVCVTTPS2DQ
	AVCVTTSD2SI
	AVCVTTSD2SIQ
	AVCVTTSS2SI
	AVCVTTSS2SIQ
	AVDIVPD
	AVDIVPS
	AVDIVSD
	AVDIVSS
	AVDPPD
	AVDPPS
	AVERR
	AVERW
	AVEXTRACTF128
	AVEXTRACTI128
	AVEXTRACTPS
	AVFMADD132PD
	AVFMADD132PS
	AVFMADD132SD
	AVFMADD132SS
	AVFMADD213PD
	AVFMADD213PS
	AVFMADD213SD
	AVFMADD213SS
	AVFMADD231PD
	AVFMADD231PS
	AVFMADD231SD
	AVFMADD231SS
	AVFMADDSUB132PD
	AVFMADDSUB132PS
	AVFMADDSUB213PD
	AVFMADDSUB213PS
	AVFMADDSUB231PD
	AVFMADDSUB231PS
	AVFMSUB132PD
	AVFMSUB132PS
	AVFMSUB132SD
	AVFMSUB132SS
	AVFMSUB213PD
	AVFMSUB213PS
	AVFMSUB213SD
	AVFMSUB213SS
	AVFMSUB231PD
	AVFMSUB231PS
	AVFMSUB231SD
	AVFMSUB231SS
	AVFMSUBADD132PD
	AVFMSUBADD132PS
	AVFMSUBADD213PD
	AVFMSUBADD213PS
	AVFMSUBADD231PD
	AVFMSUBADD231PS
	AVFNMADD132PD
	AVFNMADD132PS
	AVFNMADD132SD
	AVFNMADD132SS
	AVFNMADD213PD
	AVFNMADD213PS
	AVFNMADD213SD
	AVFNMADD213SS
	AVFNMADD231PD
	AVFNMADD231PS
	AVFNMADD231SD
	AVFNMADD231SS
	AVFNMSUB132PD
	AVFNMSUB132PS
	AVFNMSUB132SD
	AVFNMSUB132SS
	AVFNMSUB213PD
	AVFNMSUB213PS
	AVFNMSUB213SD
	AVFNMSUB213SS
	AVFNMSUB231PD
	AVFNMSUB231PS
	AVFNMSUB231SD
	AVFNMSUB231SS
	AVGATHERDPD
	AVGATHERDPS
	AVGATHERQPD
	AVGATHERQPS
	AVHADDPD
	AVHADDPS
	AVHSUBPD
	AVHSUBPS
	AVINSERTF128
	AVINSERTI128
	AVINSERTPS
	AVLDDQU
	AVLDMXCSR
	AVMASKMOVDQU
	AVMASKMOVPD
	AVMASKMOVPS
	AVMAXPD
	AVMAXPS
	AVMAXSD
	AVMAXSS
	AVMINPD
	AVMINPS
	AVMINSD
	AVMINSS
	AVMOVAPD
	AVMOVAPS
	AVMOVD
	AVMOVDDUP
	AVMOVDQA
	AVMOVDQU
	AVMOVHLPS
	AVMOVHPD
	AVMOVHPS
	AVMOVLHPS
	AVMOVLPD
	AVMOVLPS
	AVMOVMSKPD
	AVMOVMSKPS
	AVMOVNTDQ
	AVMOVNTDQA
	AVMOVNTPD
	AVMOVNTPS
	AVMOVQ
	AVMOVSD
	AVMOVSHDUP
	AVMOVSLDUP
	AVMOVSS
	AVMOVUPD
	AVMOVUPS
	AVMPSADBW
	AVMULPD
	AVMULPS
	AVMULSD
	AVMULSS
	AVORPD
	AVORPS
	AVPABSB
	AVPABSD
	AVPABSW
	AVPACKSSDW
	AVPACKSSWB
	AVPACKUSDW
	AVPACKUSWB
	AVPADDB
	AVPADDD
	AVPADDQ
	AVPADDSB
	AVPADDSW
	AVPADDUSB
	AVPADDUSW
	AVPADDW
	AVPALIGNR
	AVPAND
	AVPANDN
	AVPAVGB
	AVPAVGW
	AVPBLENDD
	AVPBLENDVB
	AVPBLENDW
	AVPBROADCASTB
	AVPBROADCASTD
	AVPBROADCASTQ
	AVPBROADCASTW
	AVPCLMULQDQ
	AVPCMPEQB
	AVPCMPEQD
	AVPCMPEQQ
	AVPCMPEQW
	AVPCMPESTRI
	AVPCMPESTRM
	AVPCMPGTB
	AVPCMPGTD
	AVPCMPGTQ
	AVPCMPGTW
	AVPCMPISTRI
	AVPCMPISTRM
	AVPERM2F128
	AVPERM2I128
	AVPERMD
	AVPERMILPD
	AVPERMILPS
	AVPERMPD
	AVPERMPS
	AVPERMQ
	AVPEXTRB
	AVPEXTRD
	AVPEXTRQ
	AVPEXTRW
	AVPGATHERDD
	AVPGATHERDQ
	AVPGATHERQD
	AVPGATHERQQ
	AVPHADDD
	AVPHADDSW
	AVPHADDW
	AVPHMINPOSUW
	AVPHSUBD
	AVPHSUBSW
	AVPHSUBW
	AVPINSRB
	AVPINSRD
	AVPINSRQ
	AVPINSRW
	AVPMADDUBSW
	AVPMADDWD
	AVPMASKMOVD
	AVPMASKMOVQ
	AVPMAXSB
	AVPMAXSD
	AVPMAXSW
	AVPMAXUB
	AVPMAXUD
	AVPMAXUW
	AVPMINSB
	AVPMINSD
	AVPMINSW
	AVPMINUB
	AVPMINUD
	AVPMINUW
	AVPMOVMSKB
	AVPMOVSXBD
	AVPMOVSXBQ
	AVPMOVSXBW
	AVPMOVSXDQ
	AVPMOVSXWD
	AVPMOVSXWQ
	AVPMOVZXBD
	AVPMOVZXBQ
	AVPMOVZXBW
	AVPMOVZXDQ
	AVPMOVZXWD
	AVPMOVZXWQ
	AVPMULDQ
	AVPMULHRSW
	AVPMULHUW
	AVPMULHW
	AVPMULLD
	AVPMULLW
	AVPMULUDQ
	AVPOR
	AVPSADBW
	AVPSHUFB
	AVPSHUFD
	AVPSHUFHW
	AVPSHUFLW
	AVPSIGNB
	AVPSIGND
	AVPSIGNW
	AVPSLLD
	AVPSLLDQ
	AVPSLLQ
	AVPSLLVD
	AVPSLLVQ
	AVPSLLW
	AVPSRAD
	AVPSRAVD
	AVPSRAW
	AVPSRLD
	AVPSRLDQ
	AVPSRLQ
	AVPSRLVD
	AVPSRLVQ
	AVPSRLW
	AVPSUBB
	AVPSUBD
	AVPSUBQ
	AVPSUBSB
	AVPSUBSW
	AVPSUBUSB
	AVPSUBUSW
	AVPSUBW
	AVPTEST
	AVPUNPCKHBW
	AVPUNPCKHDQ
	AVPUNPCKHQDQ
	AVPUNPCKHWD
	AVPUNPCKLBW
	AVPUNPCKLDQ
	AVPUNPCKLQDQ
	AVPUNPCKLWD
	AVPXOR
	AVRCPPS
	AVRCPSS
	AVROUNDPD
	AVROUNDPS
	AVROUNDSD
	AVROUNDSS
	AVRSQRTPS
	AVRSQRTSS
	AVSHUFPD
	AVSHUFPS
	AVSQRTPD
	AVSQRTPS
	AVSQRTSD
	AVSQRTSS
	AVSTMXCSR
	AVSUBPD
	AVSUBPS
	AVSUBSD
	AVSUBSS
	AVTESTPD
	AVTESTPS
	AVUCOMISD
	AVUCOMISS
	AVUNPCKHPD
	AVUNPCKHPS
	AVUNPCKLPD
	AVUNPCKLPS
	AVXORPD
	AVXORPS
	AVZEROALL
	AVZEROUPPER
	AWAIT
	AWBINVD
	AWORD
	AWRMSR
	AXABORT
	AXACQUIRE
	AXADDB
	AXADDL
	AXADDQ
	AXADDW
	AXBEGIN
	AXCHGB
	AXCHGL
	AXCHGQ
	AXCHGW
	AXEND
	AXGETBV
	AXLAT
	AXORB
	AXORL
	AXORPD
	AXORPS
	AXORQ
	AXORW
	AXRELEASE
	AXTEST
	ALAST
)
View Source
const (
	// Loop alignment constants:
	// want to align loop entry to LoopAlign-byte boundary,
	// and willing to insert at most MaxLoopPad bytes of NOP to do so.
	// We define a loop entry as the target of a backward jump.
	//
	// gcc uses MaxLoopPad = 10 for its 'generic x86-64' config,
	// and it aligns all jump targets, not just backward jump targets.
	//
	// As of 6/1/2012, the effect of setting MaxLoopPad = 10 here
	// is very slight but negative, so the alignment is disabled by
	// setting MaxLoopPad = 0. The code is here for reference and
	// for future experiments.
	//
	LoopAlign  = 16
	MaxLoopPad = 0
)
View Source
const (
	Yxxx = iota
	Ynone
	Yi0 // $0
	Yi1 // $1
	Yu2 // $x, x fits in uint2
	Yi8 // $x, x fits in int8
	Yu8 // $x, x fits in uint8
	Yu7 // $x, x in 0..127 (fits in both int8 and uint8)
	Ys32
	Yi32
	Yi64
	Yiauto
	Yal
	Ycl
	Yax
	Ycx
	Yrb
	Yrl
	Yrl32 // Yrl on 32-bit system
	Yrf
	Yf0
	Yrx
	Ymb
	Yml
	Ym
	Ybr
	Ycs
	Yss
	Yds
	Yes
	Yfs
	Ygs
	Ygdtr
	Yidtr
	Yldtr
	Ymsw
	Ytask
	Ycr0
	Ycr1
	Ycr2
	Ycr3
	Ycr4
	Ycr5
	Ycr6
	Ycr7
	Ycr8
	Ydr0
	Ydr1
	Ydr2
	Ydr3
	Ydr4
	Ydr5
	Ydr6
	Ydr7
	Ytr0
	Ytr1
	Ytr2
	Ytr3
	Ytr4
	Ytr5
	Ytr6
	Ytr7
	Ymr
	Ymm
	Yxr
	Yxm
	Yxvm // VSIB vector array; vm32x/vm64x
	Yyr
	Yym
	Yyvm // VSIB vector array; vm32y/vm64y
	Ytls
	Ytextsize
	Yindir
	Ymax
)
View Source
const (
	Zxxx = iota
	Zlit
	Zlitm_r
	Z_rp
	Zbr
	Zcall
	Zcallcon
	Zcallduff
	Zcallind
	Zcallindreg
	Zib_
	Zib_rp
	Zibo_m
	Zibo_m_xm
	Zil_
	Zil_rp
	Ziq_rp
	Zilo_m
	Zjmp
	Zjmpcon
	Zloop
	Zo_iw
	Zm_o
	Zm_r
	Zm2_r
	Zm_r_xm
	Zm_r_i_xm
	Zm_r_xm_nr
	Zr_m_xm_nr
	Zibm_r /* mmx1,mmx2/mem64,imm8 */
	Zibr_m
	Zmb_r
	Zaut_r
	Zo_m
	Zo_m64
	Zpseudo
	Zr_m
	Zr_m_xm
	Zrp_
	Z_ib
	Z_il
	Zm_ibo
	Zm_ilo
	Zib_rr
	Zil_rr
	Zbyte
	Zvex_rm_v_r
	Zvex_rm_v_ro
	Zvex_r_v_rm
	Zvex_v_rm_r
	Zvex_i_rm_r
	Zvex_i_r_v
	Zvex_i_rm_v_r
	Zvex
	Zvex_rm_r_vo
	Zvex_i_r_rm
	Zvex_hr_rm_v_r

	Zmax
)
View Source
const (
	Px   = 0
	Px1  = 1    // symbolic; exact value doesn't matter
	P32  = 0x32 /* 32-bit only */
	Pe   = 0x66 /* operand escape */
	Pm   = 0x0f /* 2byte opcode escape */
	Pq   = 0xff /* both escapes: 66 0f */
	Pb   = 0xfe /* byte operands */
	Pf2  = 0xf2 /* xmm escape 1: f2 0f */
	Pf3  = 0xf3 /* xmm escape 2: f3 0f */
	Pef3 = 0xf5 /* xmm escape 2 with 16-bit prefix: 66 f3 0f */
	Pq3  = 0x67 /* xmm escape 3: 66 48 0f */
	Pq4  = 0x68 /* xmm escape 4: 66 0F 38 */
	Pq4w = 0x69 /* Pq4 with Rex.w 66 0F 38 */
	Pq5  = 0x6a /* xmm escape 5: F3 0F 38 */
	Pq5w = 0x6b /* Pq5 with Rex.w F3 0F 38 */
	Pfw  = 0xf4 /* Pf3 with Rex.w: f3 48 0f */
	Pw   = 0x48 /* Rex.w */
	Pw8  = 0x90 // symbolic; exact value doesn't matter
	Py   = 0x80 /* defaults to 64-bit mode */
	Py1  = 0x81 // symbolic; exact value doesn't matter
	Py3  = 0x83 // symbolic; exact value doesn't matter
	Pvex = 0x84 // symbolic: exact value doesn't matter

	Rxw = 1 << 3 /* =1, 64-bit operand size */
	Rxr = 1 << 2 /* extend modrm reg */
	Rxx = 1 << 1 /* extend sib index */
	Rxb = 1 << 0 /* extend modrm r/m, sib base, or opcode reg */
)
View Source
const (

	// Combinations used in the manual.
	VEX_DDS_LIG_66_0F38_W1    = vexDDS | vexLIG | vex66 | vex0F38 | vexW1
	VEX_NDD_128_66_0F_WIG     = vexNDD | vex128 | vex66 | vex0F | vexWIG
	VEX_NDD_256_66_0F_WIG     = vexNDD | vex256 | vex66 | vex0F | vexWIG
	VEX_NDD_LZ_F2_0F38_W0     = vexNDD | vexLZ | vexF2 | vex0F38 | vexW0
	VEX_NDD_LZ_F2_0F38_W1     = vexNDD | vexLZ | vexF2 | vex0F38 | vexW1
	VEX_NDS_128_66_0F_WIG     = vexNDS | vex128 | vex66 | vex0F | vexWIG
	VEX_NDS_128_66_0F38_WIG   = vexNDS | vex128 | vex66 | vex0F38 | vexWIG
	VEX_NDS_128_F2_0F_WIG     = vexNDS | vex128 | vexF2 | vex0F | vexWIG
	VEX_NDS_256_66_0F_WIG     = vexNDS | vex256 | vex66 | vex0F | vexWIG
	VEX_NDS_256_66_0F38_WIG   = vexNDS | vex256 | vex66 | vex0F38 | vexWIG
	VEX_NDS_256_66_0F3A_W0    = vexNDS | vex256 | vex66 | vex0F3A | vexW0
	VEX_NDS_256_66_0F3A_WIG   = vexNDS | vex256 | vex66 | vex0F3A | vexWIG
	VEX_NDS_LZ_0F38_W0        = vexNDS | vexLZ | vex0F38 | vexW0
	VEX_NDS_LZ_0F38_W1        = vexNDS | vexLZ | vex0F38 | vexW1
	VEX_NDS_LZ_66_0F38_W0     = vexNDS | vexLZ | vex66 | vex0F38 | vexW0
	VEX_NDS_LZ_66_0F38_W1     = vexNDS | vexLZ | vex66 | vex0F38 | vexW1
	VEX_NDS_LZ_F2_0F38_W0     = vexNDS | vexLZ | vexF2 | vex0F38 | vexW0
	VEX_NDS_LZ_F2_0F38_W1     = vexNDS | vexLZ | vexF2 | vex0F38 | vexW1
	VEX_NDS_LZ_F3_0F38_W0     = vexNDS | vexLZ | vexF3 | vex0F38 | vexW0
	VEX_NDS_LZ_F3_0F38_W1     = vexNDS | vexLZ | vexF3 | vex0F38 | vexW1
	VEX_NOVSR_128_66_0F_WIG   = vexNOVSR | vex128 | vex66 | vex0F | vexWIG
	VEX_NOVSR_128_66_0F38_W0  = vexNOVSR | vex128 | vex66 | vex0F38 | vexW0
	VEX_NOVSR_128_66_0F38_WIG = vexNOVSR | vex128 | vex66 | vex0F38 | vexWIG
	VEX_NOVSR_128_F2_0F_WIG   = vexNOVSR | vex128 | vexF2 | vex0F | vexWIG
	VEX_NOVSR_128_F3_0F_WIG   = vexNOVSR | vex128 | vexF3 | vex0F | vexWIG
	VEX_NOVSR_256_66_0F_WIG   = vexNOVSR | vex256 | vex66 | vex0F | vexWIG
	VEX_NOVSR_256_66_0F38_W0  = vexNOVSR | vex256 | vex66 | vex0F38 | vexW0
	VEX_NOVSR_256_66_0F38_WIG = vexNOVSR | vex256 | vex66 | vex0F38 | vexWIG
	VEX_NOVSR_256_F2_0F_WIG   = vexNOVSR | vex256 | vexF2 | vex0F | vexWIG
	VEX_NOVSR_256_F3_0F_WIG   = vexNOVSR | vex256 | vexF3 | vex0F | vexWIG
	VEX_NOVSR_LZ_F2_0F3A_W0   = vexNOVSR | vexLZ | vexF2 | vex0F3A | vexW0
	VEX_NOVSR_LZ_F2_0F3A_W1   = vexNOVSR | vexLZ | vexF2 | vex0F3A | vexW1
)
View Source
const (
	/* mark flags */
	DONE = 1 << iota
)
View Source
const (
	E = 0xff
)
View Source
const (
	REG_NONE = 0
)

Variables

View Source
var AMD64DWARFRegisters = map[int16]int16{
	REG_AX:  0,
	REG_DX:  1,
	REG_CX:  2,
	REG_BX:  3,
	REG_SI:  4,
	REG_DI:  5,
	REG_BP:  6,
	REG_SP:  7,
	REG_R8:  8,
	REG_R9:  9,
	REG_R10: 10,
	REG_R11: 11,
	REG_R12: 12,
	REG_R13: 13,
	REG_R14: 14,
	REG_R15: 15,

	REG_X0:  17,
	REG_X1:  18,
	REG_X2:  19,
	REG_X3:  20,
	REG_X4:  21,
	REG_X5:  22,
	REG_X6:  23,
	REG_X7:  24,
	REG_X8:  25,
	REG_X9:  26,
	REG_X10: 27,
	REG_X11: 28,
	REG_X12: 29,
	REG_X13: 30,
	REG_X14: 31,
	REG_X15: 32,

	REG_F0: 33,
	REG_F1: 34,
	REG_F2: 35,
	REG_F3: 36,
	REG_F4: 37,
	REG_F5: 38,
	REG_F6: 39,
	REG_F7: 40,

	REG_M0: 41,
	REG_M1: 42,
	REG_M2: 43,
	REG_M3: 44,
	REG_M4: 45,
	REG_M5: 46,
	REG_M6: 47,
	REG_M7: 48,

	REG_ES: 50,
	REG_CS: 51,
	REG_SS: 52,
	REG_DS: 53,
	REG_FS: 54,
	REG_GS: 55,

	REG_TR:   62,
	REG_LDTR: 63,
}

https://www.uclibc.org/docs/psABI-x86_64.pdf, figure 3.36

View Source
var Anames = []string{}/* 1126 elements not displayed */
View Source
var Link386 = obj.LinkArch{
	Arch:           sys.Arch386,
	Init:           instinit,
	Preprocess:     preprocess,
	Assemble:       span6,
	Progedit:       progedit,
	UnaryDst:       unaryDst,
	DWARFRegisters: X86DWARFRegisters,
}
View Source
var Linkamd64 = obj.LinkArch{
	Arch:           sys.ArchAMD64,
	Init:           instinit,
	Preprocess:     preprocess,
	Assemble:       span6,
	Progedit:       progedit,
	UnaryDst:       unaryDst,
	DWARFRegisters: AMD64DWARFRegisters,
}
View Source
var Linkamd64p32 = obj.LinkArch{
	Arch:           sys.ArchAMD64P32,
	Init:           instinit,
	Preprocess:     preprocess,
	Assemble:       span6,
	Progedit:       progedit,
	UnaryDst:       unaryDst,
	DWARFRegisters: AMD64DWARFRegisters,
}
View Source
var Register = []string{}/* 129 elements not displayed */
View Source
var X86DWARFRegisters = map[int16]int16{
	REG_AX: 0,
	REG_CX: 1,
	REG_DX: 2,
	REG_BX: 3,
	REG_SP: 4,
	REG_BP: 5,
	REG_SI: 6,
	REG_DI: 7,

	REG_F0: 11,
	REG_F1: 12,
	REG_F2: 13,
	REG_F3: 14,
	REG_F4: 15,
	REG_F5: 16,
	REG_F6: 17,
	REG_F7: 18,

	REG_X0: 21,
	REG_X1: 22,
	REG_X2: 23,
	REG_X3: 24,
	REG_X4: 25,
	REG_X5: 26,
	REG_X6: 27,
	REG_X7: 28,

	REG_M0: 29,
	REG_M1: 30,
	REG_M2: 31,
	REG_M3: 32,
	REG_M4: 33,
	REG_M5: 34,
	REG_M6: 35,
	REG_M7: 36,

	REG_ES:   40,
	REG_CS:   41,
	REG_SS:   42,
	REG_DS:   43,
	REG_FS:   44,
	REG_GS:   45,
	REG_TR:   48,
	REG_LDTR: 49,
}

https://www.uclibc.org/docs/psABI-i386.pdf, table 2.14

Functions

func CanUse1InsnTLS

func CanUse1InsnTLS(ctxt *obj.Link) bool

Types

type AsmBuf

type AsmBuf struct {
	// contains filtered or unexported fields
}

AsmBuf is a simple buffer to assemble variable-length x86 instructions into and hold assembly state.

func (*AsmBuf) At

func (a *AsmBuf) At(i int) byte

At returns the byte at offset i.

func (*AsmBuf) Bytes

func (a *AsmBuf) Bytes() []byte

Bytes returns the contents of the buffer.

func (*AsmBuf) Insert

func (a *AsmBuf) Insert(i int, b byte)

Insert inserts b at offset i.

func (*AsmBuf) Last

func (a *AsmBuf) Last() byte

Last returns the byte at the end of the buffer.

func (*AsmBuf) Len

func (a *AsmBuf) Len() int

Len returns the length of the buffer.

func (*AsmBuf) Put

func (a *AsmBuf) Put(b []byte)

Put copies b into the buffer.

func (*AsmBuf) Put1

func (a *AsmBuf) Put1(x byte)

Put1 appends one byte to the end of the buffer.

func (*AsmBuf) Put2

func (a *AsmBuf) Put2(x, y byte)

Put2 appends two bytes to the end of the buffer.

func (*AsmBuf) Put3

func (a *AsmBuf) Put3(x, y, z byte)

Put3 appends three bytes to the end of the buffer.

func (*AsmBuf) Put4

func (a *AsmBuf) Put4(x, y, z, w byte)

Put4 appends four bytes to the end of the buffer.

func (*AsmBuf) PutInt16

func (a *AsmBuf) PutInt16(v int16)

PutInt16 writes v into the buffer using little-endian encoding.

func (*AsmBuf) PutInt32

func (a *AsmBuf) PutInt32(v int32)

PutInt32 writes v into the buffer using little-endian encoding.

func (*AsmBuf) PutInt64

func (a *AsmBuf) PutInt64(v int64)

PutInt64 writes v into the buffer using little-endian encoding.

func (*AsmBuf) Reset

func (a *AsmBuf) Reset()

Reset empties the buffer.

type Movtab

type Movtab struct {
	// contains filtered or unexported fields
}

type Optab

type Optab struct {
	// contains filtered or unexported fields
}

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