arm

Documentation

Overview

Package arm provides support for ARM architecture specific operations.

The following architectures/cores are supported/tested:

• ARMv7-A / Cortex-A7 (single-core)

This package is only meant to be used with `GOOS=tamago GOARCH=arm` as supported by the TamaGo framework for bare metal Go on ARM SoCs, see https://github.com/f-secure-foundry/tamago.

Index

• Constants
• Variables
• func Busyloop(count int32)
• func DefaultExceptionHandler(off int)
• func InitGIC(base uint32)
• func ModeName(mode int) string
• func SetVectorTable(t VectorTable)
• func VectorName(off int) string
• type CPU
  • func (cpu *CPU) ConfigureMMU(start uint32, end uint32, flags uint32)
  • func (cpu *CPU) DebugStatus() uint32
  • func (cpu *CPU) DisableCache()
  • func (cpu *CPU) DisableInterrupts()
  • func (cpu *CPU) EnableCache()
  • func (cpu *CPU) EnableInterrupts()
  • func (cpu *CPU) EnableSMP()
  • func (cpu *CPU) EnableVFP()
  • func (cpu *CPU) FlushDataCache()
  • func (cpu *CPU) FlushInstructionCache()
  • func (cpu *CPU) Init()
  • func (cpu *CPU) InitGenericTimers(base uint32, freq int32)
  • func (cpu *CPU) InitGlobalTimers()
  • func (cpu *CPU) InitMMU()
  • func (cpu *CPU) Mode() int
  • func (cpu *CPU) NonSecure() bool
  • func (cpu *CPU) NonSecureAccessControl(nsacr uint32)
  • func (cpu *CPU) Secure() bool
  • func (cpu *CPU) SetTimerOffset(offset int64)
• type ExceptionHandler
• type VectorTable
  • func SystemVectorTable() VectorTable

Constants

const (
	USR_MODE = 0b10000
	FIQ_MODE = 0b10001
	IRQ_MODE = 0b10010
	SVC_MODE = 0b10011
	MON_MODE = 0b10110
	ABT_MODE = 0b10111
	HYP_MODE = 0b11010
	UND_MODE = 0b11011
	SYS_MODE = 0b11111
)

ARM processor modes (Table B1-1, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

const (
	RESET          = 0x00
	UNDEFINED      = 0x04
	SUPERVISOR     = 0x08
	PREFETCH_ABORT = 0x0c
	DATA_ABORT     = 0x10
	IRQ            = 0x18
	FIQ            = 0x1c
)

ARM exception vector offsets (Table 11-1, ARM® Cortex™ -A Series Programmer’s Guide).

const (
	ID_PFR0_ARM_MASK     = 0x000f
	ID_PFR0_THUMB_MASK   = 0x00f0
	ID_PFR0_THUMBEE_MASK = 0x0f00
	ID_PFR0_JAZELLE_MASK = 0xf000

	ID_PFR1_PROGRAMMERS_MODEL_MASK = 0x0000f
	ID_PFR1_SECURITY_MASK          = 0x000f0
	ID_PFR1_M_PROFILE_MODEL_MASK   = 0x00f00
	ID_PFR1_VIRTUALIZATION_MASK    = 0x0f000
	ID_PFR1_GENERIC_TIMER_MASK     = 0xf0000
)

ARM processor feature registers

const (
	// GIC offsets in Cortex-A7
	// (p178, Table 8-1, Cortex-A7 MPCore Technical Reference Manual).
	GICD_OFF = 0x1000
	GICC_OFF = 0x2000

	// Distributor register map
	// (p75, Table 4-1, ARM Generic Interrupt Controller Architecture Specification).
	GICD_CTLR            = 0
	GICD_CTLR_ENABLEGRP1 = 1
	GICD_CTLR_ENABLEGRP0 = 0

	GICD_TYPER         = 0x4
	GICD_TYPER_ITLINES = 0

	GICD_IGROUPR   = 0x080
	GICD_ICENABLER = 0x180
	GICD_ICPENDR   = 0x280

	// CPU interface register map
	// (p76, Table 4-2, ARM Generic Interrupt Controller Architecture Specification).
	GICC_CTLR            = 0
	GICC_CTLR_FIQEN      = 3
	GICC_CTLR_ENABLEGRP1 = 1
	GICC_CTLR_ENABLEGRP0 = 0

	GICC_PMR          = 0x4
	GICC_PMR_PRIORITY = 0
)

const (
	TTE_PAGE_TABLE    uint32 = (1 << 0)
	TTE_SECTION       uint32 = (1 << 1)
	TTE_BUFFERABLE    uint32 = (1 << 2)
	TTE_CACHEABLE     uint32 = (1 << 3)
	TTE_EXECUTE_NEVER uint32 = (1 << 4)
	TTE_SUPERSECTION  uint32 = (1 << 18) | (1 << 1)
	TTE_NS            uint32 = (1 << 19)
)

Memory region attributes (Table B3-10, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

const (
	// PL1: no access   PL0: no access
	TTE_AP_000 uint32 = 0b000
	// PL1: read/write  PL0: no access
	TTE_AP_001 uint32 = 0b001
	// PL1: read/write  PL0: read only
	TTE_AP_010 uint32 = 0b010
	// PL1: read/write  PL0: read/write
	TTE_AP_011 uint32 = 0b011
	// Reserved
	TTE_AP_100 uint32 = 0b100
	// PL1: read only   PL0: no access
	TTE_AP_101 uint32 = 0b101
	// PL1: read only   PL0: read only
	TTE_AP_110 uint32 = 0b110
	// PL1: read only   PL0: read only
	TTE_AP_111 uint32 = 0b111
)

MMU access permissions (Table B3-8, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

const (
	// p2402, Table D5-1, ARMv7 Architecture Reference Manual
	CNTCR = 0
	// base frequency
	CNTFID0 = 0x20

	// p2410, D5.7.2 CNTCR, Counter Control Register, ARMv7 Architecture
	// Reference Manual
	//
	// frequency = CNTFID0/CNTFID2
	CNTCR_FCREQ2 = 10
	// frequency = CNTFID0/CNTFID1
	CNTCR_FCREQ1 = 9
	// frequency = CNTFID0
	CNTCR_FCREQ0 = 8
	CNTCR_HDBG   = 1
	CNTCR_EN     = 0

	CNTKCTL_PL0PCTEN = 0
)

ARM timer register constants

const (
	ACTLR_SMP = 6
)

ARM cache register constants

const (
	FPEXC_EN = 30
)

Variables

var SystemExceptionHandler = DefaultExceptionHandler

SystemExceptionHandler allows to override the default exception handler executed at any exception by the table returned by SystemVectorTable(), which is used by default when initializing the CPU instance (e.g. CPU.Init()).

Functions

func Busyloop

func Busyloop(count int32)

Busyloop spins the processor for busy waiting purposes, taking a counter value for the number of loops.

func DefaultExceptionHandler

func DefaultExceptionHandler(off int)

DefaultExceptionHandler handles an exception by printing its vector and processor mode before panicking.

func InitGIC

func InitGIC(base uint32)

InitGIC initializes the ARM Generic Interrupt Controller (GIC).

func ModeName

func ModeName(mode int) string

ModeName returns the processor mode name.

func SetVectorTable

func SetVectorTable(t VectorTable)

SetVectorTable updates the CPU exception handling vector table with the addresses of the functions defined in the passed structure.

func VectorName

func VectorName(off int) string

VectorName returns the exception vector offset name.

Types

type CPU

type CPU struct {

	// timer multiplier
	TimerMultiplier int64
	// timer offset in nanoseconds
	TimerOffset int64
	// timer function
	TimerFn func() int64
	// contains filtered or unexported fields
}

CPU instance

func (*CPU) ConfigureMMU

func (cpu *CPU) ConfigureMMU(start uint32, end uint32, flags uint32)

ConfigureMMU (re)configures the first-level translation tables for the provided memory range with the passed attribute flags.

func (*CPU) DebugStatus

func (cpu *CPU) DebugStatus() uint32

DebugStatus returns the contents of the ARM DBGAUTHSTATUS register, useful to get the current state of the processor debug permissions (C11.11.1, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition).

func (*CPU) DisableCache

func (cpu *CPU) DisableCache()

DisableCache disables the ARM instruction and data caches.

func (*CPU) DisableInterrupts

func (cpu *CPU) DisableInterrupts()

DisableInterrupts disables IRQ and FIQ interrupts.

func (*CPU) EnableCache

func (cpu *CPU) EnableCache()

EnableCache activates the ARM instruction and data caches.

func (*CPU) EnableInterrupts

func (cpu *CPU) EnableInterrupts()

EnableInterrupts enables IRQ and FIQ interrupts.

func (*CPU) EnableSMP

func (cpu *CPU) EnableSMP()

EnableSMP sets the SMP bit in Cortex-A7 Auxiliary Control Register, to enable coherent requests to the processor. This must be ensured before caches and MMU are enabled or any cache and TLB maintenance operations are performed (p115, Cortex™-A7 MPCore® Technical Reference Manual r0p5).

func (*CPU) EnableVFP

func (cpu *CPU) EnableVFP()

EnableVFP activates the ARM Vector-Floating-Point co-processor.

func (*CPU) FlushDataCache

func (cpu *CPU) FlushDataCache()

FlushDataCache flushes the ARM data cache.

func (*CPU) FlushInstructionCache

func (cpu *CPU) FlushInstructionCache()

FlushInstructionCache flushes the ARM instruction cache.

func (*CPU) Init

func (cpu *CPU) Init()

Init performs initialization of an ARM core instance.

func (*CPU) InitGenericTimers

func (cpu *CPU) InitGenericTimers(base uint32, freq int32)

InitGenericTimers initializes ARM Cortex-A7 timers.

func (*CPU) InitGlobalTimers

func (cpu *CPU) InitGlobalTimers()

InitGlobalTimers initializes ARM Cortex-A9 timers.

func (*CPU) InitMMU

func (cpu *CPU) InitMMU()

InitMMU initializes the first-level translation tables for all available memory with a flat mapping and privileged attribute flags.

The first 4096 bytes (0x00000000 - 0x00001000) are flagged as invalid to trap null pointers, applications that need to make use of this memory space must use ConfigureMMU to reconfigure as required.

func (*CPU) Mode

func (cpu *CPU) Mode() int

Mode returns the processor mode.

func (*CPU) NonSecure

func (cpu *CPU) NonSecure() bool

NonSecure returns whether the processor security mode is non-secure (e.g. TrustZone Normal World.

func (*CPU) NonSecureAccessControl

func (cpu *CPU) NonSecureAccessControl(nsacr uint32)

NonSecureAccessControl sets the NSACR register value, which defines the Non-Secure access permissions to coprocessors.

func (*CPU) Secure

func (cpu *CPU) Secure() bool

Secure returns whether the processor security mode is secure (e.g. TrustZone Secure World).

func (*CPU) SetTimerOffset

func (cpu *CPU) SetTimerOffset(offset int64)

SetTimerOffset sets the timer offset in nanoseconds.

type ExceptionHandler

type ExceptionHandler func()

type VectorTable

type VectorTable struct {
	Reset         ExceptionHandler
	Undefined     ExceptionHandler
	Supervisor    ExceptionHandler
	PrefetchAbort ExceptionHandler
	DataAbort     ExceptionHandler
	IRQ           ExceptionHandler
	FIQ           ExceptionHandler
}

func SystemVectorTable

func SystemVectorTable() VectorTable

SystemVectorTable returns a vector table that, for all exceptions, switches to system mode and calls the SystemExceptionHandler on the Go runtime stack within goroutine g0.