imx6

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 Go to latest Published: Mar 7, 2022 License: BSD-3-Clause Imports: 11 Imported by: 0

README

TamaGo - bare metal Go for ARM SoCs - i.MX 6 support

tamago | https://github.com/f-secure-foundry/tamago

Copyright (c) F-Secure Corporation
https://foundry.f-secure.com

TamaGo gopher

Authors

Andrea Barisani
andrea.barisani@f-secure.com | andrea@inversepath.com

Andrej Rosano
andrej.rosano@f-secure.com | andrej@inversepath.com

Introduction

TamaGo is a framework that enables compilation and execution of unencumbered Go applications on bare metal ARM System-on-Chip (SoC) components.

The imx6 package provides support for NXP i.MX 6 series of System-on-Chip (SoCs) parts.

Documentation

For TamaGo see its repository and project wiki for information.

The package API documentation can be found on pkg.go.dev.

Supported hardware

SoC Related board packages Peripheral drivers
NXP i.MX 6UltraLite usbarmory/mark-two DCP, GPIO, I2C, RNGB, UART, USB, USDHC, OCOTP, CSU, TZASC

License

tamago | https://github.com/f-secure-foundry/tamago
Copyright (c) F-Secure Corporation

These source files are distributed under the BSD-style license found in the LICENSE file.

The TamaGo logo is adapted from the Go gopher designed by Renee French and licensed under the Creative Commons 3.0 Attributions license. Go Gopher vector illustration by Hugo Arganda.

Documentation

Overview

Package imx6 provides support to Go bare metal unikernels written using the TamaGo framework.

The package implements initialization and drivers for specific NXP i.MX6 System-on-Chip (SoC) peripherals, adopting, where indicated, the following reference specifications:

  • IMX6ULLRM - i.MX 6ULL Applications Processor Reference Manual - Rev 1 2017/11
  • IMX6FG - i.MX 6 Series Firmware Guide - Rev 0 2012/11
  • IMX6ULLCEC - i.MX6ULL Data Sheet - Rev 1.2 2017/11
  • MCIMX28RM - i.MX28 Applications Processor Reference Manual - Rev 2 2013/08
  • SD-PL-7.10 - SD Specifications Part 1 Physical Layer Simplified Specification - 7.10 2020/03/25
  • JESD84-B51 - Embedded Multi-Media Card (e•MMC) Electrical Standard (5.1) - JESD84-B51 2015/02
  • USB2.0 - USB Specification Revision 2.0 - 2.0 2000/04/27

This package is only meant to be used with `GOOS=tamago GOARCH=arm` as supported by the TamaGo framework for bare metal Go on ARM SoCs, see https://github.com/f-secure-foundry/tamago.

Index

Constants

View Source 
const (
	CCM_CACRR      = 0x020c4010
	CACRR_ARM_PODF = 0

	CCM_CBCDR      = 0x020c4014
	CBCDR_IPG_PODF = 8

	CCM_CSCDR1             = 0x020c4024
	CSCDR1_USDHC2_CLK_PODF = 16
	CSCDR1_USDHC1_CLK_PODF = 11
	CSCDR1_UART_CLK_SEL    = 6
	CSCDR1_UART_CLK_PODF   = 0

	CCM_CSCMR1            = 0x020c401c
	CSCMR1_USDHC2_CLK_SEL = 17
	CSCMR1_USDHC1_CLK_SEL = 16
	CSCMR1_PERCLK_SEL     = 6
	CSCMR1_PERCLK_PODF    = 0

	CCM_ANALOG_PLL_ARM = 0x020c8000
	PLL_LOCK           = 31
	PLL_BYPASS         = 16
	PLL_BYPASS_CLK_SRC = 14
	PLL_ENABLE         = 13
	PLL_POWER          = 12
	PLL_DIV_SELECT     = 0

	CCM_ANALOG_PLL_USB1 = CCM_ANALOG_PLL_ARM + 0x10
	CCM_ANALOG_PLL_USB2 = CCM_ANALOG_PLL_ARM + 0x20
	PLL_EN_USB_CLKS     = 6

	CCM_ANALOG_PFD_480  = 0x020c80f0
	CCM_ANALOG_PFD_528  = 0x020c8100
	ANALOG_PFD3_CLKGATE = 31
	ANALOG_PFD3_FRAC    = 24
	ANALOG_PFD2_CLKGATE = 23
	ANALOG_PFD2_FRAC    = 16
	ANALOG_PFD1_CLKGATE = 15
	ANALOG_PFD1_FRAC    = 8
	ANALOG_PFD0_CLKGATE = 7
	ANALOG_PFD0_FRAC    = 0

	PMU_REG_CORE   = 0x020c8140
	CORE_REG2_TARG = 18
	CORE_REG0_TARG = 0

	CCM_CCGR1 = 0x020c406c
	CCM_CCGR2 = 0x020c4070
	CCM_CCGR6 = 0x020c4080

	CCGRx_CG15 = 30
	CCGRx_CG14 = 28
	CCGRx_CG13 = 26
	CCGRx_CG12 = 24
	CCGRx_CG11 = 22
	CCGRx_CG10 = 20
	CCGRx_CG9  = 18
	CCGRx_CG8  = 16
	CCGRx_CG7  = 14
	CCGRx_CG6  = 12
	CCGRx_CG5  = 10
	CCGRx_CG4  = 8
	CCGRx_CG3  = 6
	CCGRx_CG2  = 4
	CCGRx_CG1  = 2
	CCGRx_CG0  = 0
)

Clock registers

View Source 
const (
	OSC_FREQ  = 24000000
	PLL2_FREQ = 528000000
	PLL3_FREQ = 480000000
)

Oscillator frequencies

View Source 
const (
	FreqMax = Freq900
	Freq900 = 900
	Freq792 = 792
	Freq528 = 528
	Freq396 = 396
	Freq198 = 198
	FreqLow = Freq198
)

Operating ARM core frequencies in MHz (p24, Table 10. Operating Ranges, IMX6ULLCEC).

View Source 
const (
	IOMUXC_GPR_GPR10 = 0x020e4028
	GPR10_DBG_CLK_EN = 1
	GPR10_DBG_EN     = 0
)
View Source 
const (
	IRAMStart uint32 = 0x00900000
	IRAMSize         = 0x20000
)
View Source 
const (
	GPIO1_BASE = 0x0209c000
	GPIO2_BASE = 0x020a0000
	GPIO3_BASE = 0x020a4000
	GPIO4_BASE = 0x020a8000

	GPIO_DR   = 0x00
	GPIO_GDIR = 0x04

	GPIO_MODE = 5
)

GPIO constants

View Source 
const (

	// i.MX 6UltraLite (G0, G1, G2, G3, G4)
	// i.MX 6ULL (Y0, Y1, Y2)
	// i.MX 6ULZ (Z0)
	I2C1_BASE = 0x021a0000
	I2C2_BASE = 0x021a4000

	// i.MX 6UltraLite (G1, G2, G3, G4)
	// i.MX 6ULL (Y1, Y2)
	I2C3_BASE = 0x021a8000
	I2C4_BASE = 0x021f8000

	I2Cx_IADR = 0x0000
	I2Cx_IFDR = 0x0004

	I2Cx_I2CR = 0x0008
	I2CR_IEN  = 7
	I2CR_MSTA = 5
	I2CR_MTX  = 4
	I2CR_TXAK = 3
	I2CR_RSTA = 2

	I2Cx_I2SR = 0x000c
	I2SR_IBB  = 5
	I2SR_IIF  = 1
	I2SR_RXAK = 0

	I2Cx_I2DR = 0x0010
)

I2C registers

View Source 
const (
	OCOTP_CFG0         = 0x021bc410
	OCOTP_CFG1         = 0x021bc420
	USB_ANALOG_DIGPROG = 0x020c8260
)

Identification registers

View Source 
const (
	// GIC base address (p176, Table 2-1, IMX6ULLRM)
	GIC_BASE = 0x00a00000

	// Timer registers (p178, Table 2-3, IMX6ULLRM)
	SYS_CNT_BASE = 0x021dc000
)
View Source 
const (
	IMX6UL  = 0x64
	IMX6ULL = 0x65
)

i.MX processor families

View Source 
const (
	IOMUXC_START = 0x020e0000
	IOMUXC_END   = 0x020e3fff

	SW_PAD_CTL_HYS = 16

	SW_PAD_CTL_PUS                = 14
	SW_PAD_CTL_PUS_PULL_DOWN_100K = 0b00
	SW_PAD_CTL_PUS_PULL_UP_47K    = 0b01
	SW_PAD_CTL_PUS_PULL_UP_100K   = 0b10
	SW_PAD_CTL_PUS_PULL_UP_22K    = 0b11

	SW_PAD_CTL_PUE = 13
	SW_PAD_CTL_PKE = 12
	SW_PAD_CTL_ODE = 11

	SW_PAD_CTL_SPEED        = 6
	SW_PAD_CTL_SPEED_50MHZ  = 0b00
	SW_PAD_CTL_SPEED_100MHZ = 0b10
	SW_PAD_CTL_SPEED_200MHZ = 0b11

	SW_PAD_CTL_DSE                        = 3
	SW_PAD_CTL_DSE_OUTPUT_DRIVER_DISABLED = 0b000
	SW_PAD_CTL_DSE_2_R0_2                 = 0b010
	SW_PAD_CTL_DSE_2_R0_3                 = 0b011
	SW_PAD_CTL_DSE_2_R0_4                 = 0b100
	SW_PAD_CTL_DSE_2_R0_5                 = 0b101
	SW_PAD_CTL_DSE_2_R0_6                 = 0b110
	SW_PAD_CTL_DSE_2_R0_7                 = 0b111

	SW_PAD_CTL_SRE = 0

	SW_MUX_CTL_SION     = 4
	SW_MUX_CTL_MUX_MODE = 0
)

IOMUX registers

View Source 
const (
	SNVS_HPSR_REG       = 0x020cc014
	HPSR_OTPMK_ZERO     = 27
	HPSR_OTPMK_SYNDROME = 16

	HPSR_SSM_STATE    = 8
	SSM_STATE_TRUSTED = 0b1101
	SSM_STATE_SECURE  = 0b1111
)
View Source 
const (
	UART_DEFAULT_BAUDRATE = 115200
	ESC                   = 0x1b

	// i.MX 6UltraLite (G0, G1, G2, G3, G4)
	// i.MX 6ULL (Y0, Y1, Y2)
	// i.MX 6ULZ (Z0)
	UART1_BASE = 0x02020000
	UART2_BASE = 0x021e8000
	UART3_BASE = 0x021ec000
	UART4_BASE = 0x021f0000

	// i.MX 6UltraLite (G1, G2, G3, G4)
	// i.MX 6ULL (Y1, Y2)
	UART5_BASE = 0x021f4000
	UART6_BASE = 0x021fc000
	UART7_BASE = 0x02018000
	UART8_BASE = 0x02024000

	UARTx_URXD   = 0x0000
	URXD_CHARRDY = 15
	URXD_ERR     = 14
	URXD_OVRRUN  = 13
	URXD_FRMERR  = 12
	URXD_BRK     = 11
	URXD_PRERR   = 10
	URXD_RX_DATA = 0

	UARTx_UTXD   = 0x0040
	UTXD_TX_DATA = 0

	UARTx_UCR1    = 0x0080
	UCR1_ADEN     = 15
	UCR1_ADBR     = 14
	UCR1_TRDYEN   = 13
	UCR1_IDEN     = 12
	UCR1_ICD      = 10
	UCR1_RRDYEN   = 9
	UCR1_RXDMAEN  = 8
	UCR1_IREN     = 7
	UCR1_TXMPTYEN = 6
	UCR1_RTSDEN   = 5
	UCR1_SNDBRK   = 4
	UCR1_TXDMAEN  = 3
	UCR1_ATDMAEN  = 2
	UCR1_DOZE     = 1
	UCR1_UARTEN   = 0

	UARTx_UCR2 = 0x0084
	UCR2_ESCI  = 15
	UCR2_IRTS  = 14
	UCR2_CTSC  = 13
	UCR2_CTS   = 12
	UCR2_ESCEN = 11
	UCR2_RTEC  = 9
	UCR2_PREN  = 8
	UCR2_PROE  = 7
	UCR2_STPB  = 6
	UCR2_WS    = 5
	UCR2_RTSEN = 4
	UCR2_ATEN  = 3
	UCR2_TXEN  = 2
	UCR2_RXEN  = 1
	UCR2_SRST  = 0

	UARTx_UCR3     = 0x0088
	UCR3_DPEC      = 14
	UCR3_DTREN     = 13
	UCR3_PARERREN  = 12
	UCR3_FRAERREN  = 11
	UCR3_DSR       = 10
	UCR3_DCD       = 9
	UCR3_RI        = 8
	UCR3_ADNIMP    = 7
	UCR3_RXDSEN    = 6
	UCR3_AIRINTEN  = 5
	UCR3_AWAKEN    = 4
	UCR3_DTRDEN    = 3
	UCR3_RXDMUXSEL = 2
	UCR3_INVT      = 1
	UCR3_ACIEN     = 0

	UARTx_UCR4 = 0x008c
	UCR4_CTSTL = 10

	UARTx_UFCR  = 0x0090
	UFCR_TXTL   = 10
	UFCR_RFDIV  = 7
	UFCR_DCEDTE = 6
	UFCR_RXTL   = 0

	UARTx_USR2 = 0x0098
	USR2_RDR   = 0

	UARTx_UESC = 0x009c
	UARTx_UTIM = 0x00a0
	UARTx_UBIR = 0x00a4
	UARTx_UBMR = 0x00a8

	UARTx_UTS  = 0x00b4
	UTS_TXFULL = 4
)

UART registers

View Source 
const (
	WDOG1_WCR  = 0x020bc000
	WDOG1_WMCR = 0x020bc008

	WDOG2_WCR  = 0x020c0000
	WDOG2_WMCR = 0x020c0008

	WDOG3_WCR  = 0x021e4000
	WDOG3_WMCR = 0x021e4008

	WCR_SRE  = 6
	WCR_WDA  = 5
	WCR_SRS  = 4
	WMCR_PDE = 0
)

Watchdog control registers, 32-bit access should be avoided as all registers are 16-bit.

View Source 
const (
	SRC_SCR               = 0x020d8000
	SCR_WARM_RESET_ENABLE = 0
)

System Reset Controller registers

Variables

View Source 
var ARM = &arm.CPU{}

ARM processor instance

View Source 
var Family uint32

Processor family

View Source 
var I2C1 = &I2C{n: 1}

I2C1 instance

View Source 
var I2C2 = &I2C{n: 2}

I2C2 instance

View Source 
var Native bool

Flag for native or emulated processor

View Source 
var UART1 = &UART{
	n:        1,
	Baudrate: UART_DEFAULT_BAUDRATE,
}

UART1 instance

View Source 
var UART2 = &UART{
	n:        2,
	Baudrate: UART_DEFAULT_BAUDRATE,
}

UART2 instance

Functions

func ARMCoreDiv 

func ARMCoreDiv() (div float32)

ARMCoreDiv returns the ARM core divider value (p665, 18.6.5 CCM Arm Clock Root Register, IMX6ULLRM).

func ARMFreq 

func ARMFreq() (hz uint32)

ARMFreq returns the ARM core frequency.

func ARMPLLDiv 

func ARMPLLDiv() (div float32)

ARMPLLDiv returns the ARM PLL divider value (p714, 18.7.1 Analog ARM PLL control Register, IMX6ULLRM).

func DisableDebug 

func DisableDebug()

DisableDebug disables the ARM invasive and non-invasive debug functionality.

func EnableDebug 

func EnableDebug()

EnableDebug enables the ARM invasive and non-invasive debug functionality.

func GetPFD 

func GetPFD(pll int, pfd int) (div uint32, hz uint32)

GetPFD returns the fractional divider and frequency in Hz of a PLL PFD (p734, 18.7.15 480MHz Clock (PLL3) Phase Fractional Divider Control Register, IMX6ULLRM) (p736, 18.7.16 480MHz Clock (PLL2) Phase Fractional Divider Control Register, IMX6ULLRM).

func Init 

func Init()

Init takes care of the lower level SoC initialization triggered early in runtime setup.

func Model 

func Model() (model string)

Model returns the SoC model name.

func Reset 

func Reset()

Reset asserts the global watchdog reset causing the SoC to restart (warm reset).

Note that only the SoC itself is guaranteed to restart as, depending on the board hardware layout, the system might remain powered (which might not be desirable). See respective board packages for cold reset options.

func SNVS 

func SNVS() bool

SNVS verifies whether the Secure Non Volatile Storage (SNVS) is available in Trusted or Secure state (indicating that Secure Boot is enabled).

The unique OTPMK internal key is available only when Secure Boot (HAB) is enabled, otherwise a Non-volatile Test Key (NVTK), identical for each SoC, is used.

func SetARMFreq 

func SetARMFreq(mhz uint32) (err error)

SetARMFreq changes the ARM core frequency, see `Freq*` constants for supported values.

func SetPFD 

func SetPFD(pll uint32, pfd uint32, div uint32) error

SetPFD sets the fractional divider of a PPL PFD (p734, 18.7.15 480MHz Clock (PLL3) Phase Fractional Divider Control Register, IMX6ULLRM) (p736, 18.7.16 480MHz Clock (PLL2) Phase Fractional Divider Control Register, IMX6ULLRM).

func SetRNG 

func SetRNG(getRandomData func([]byte))

SetRNG allows to override the random number generator function selected internally by TamaGo as runtime.getRandomData.

At runtime initialization the imx6 package selects either the NXP True Random Number Generator (RNGB) driver or a timer seeded LCG, depending whether a real or emulated SoC is detected.

func SiliconVersion 

func SiliconVersion() (sv, family, revMajor, revMinor uint32)

SiliconVersion returns the SoC silicon version information (p3945, 57.4.11 Chip Silicon Version (USB_ANALOG_DIGPROG), IMX6ULLRM).

func UniqueID 

func UniqueID() (uid [8]byte)

UniqueID returns the NXP SoC Device Unique 64-bit ID.

Types

type GPIO 

type GPIO struct {
	Pad *Pad
	// contains filtered or unexported fields
}

GPIO instance

func NewGPIO 

func NewGPIO(num int, instance int, mux uint32, pad uint32) (gpio *GPIO, err error)

NewGPIO initializes a pad for GPIO mode.

func (*GPIO) High 

func (gpio *GPIO) High()

High configures a GPIO signal as high.

func (*GPIO) In 

func (gpio *GPIO) In()

In configures a GPIO as input.

func (*GPIO) Low 

func (gpio *GPIO) Low()

Low configures a GPIO signal as low.

func (*GPIO) Out 

func (gpio *GPIO) Out()

Out configures a GPIO as output.

func (*GPIO) Value 

func (gpio *GPIO) Value() (high bool)

Value returns the GPIO signal level.

type I2C 

type I2C struct {
	sync.Mutex

	// Timeout for I2C operations
	Timeout time.Duration
	// contains filtered or unexported fields
}

I2C represents a I2C port instance.

func (*I2C) Init 

func (hw *I2C) Init()

Init initializes the I2C controller instance. At this time only master mode is supported by this driver.

func (*I2C) Read 

func (hw *I2C) Read(slave uint8, addr uint32, alen int, size int) (buf []byte, err error)

Read reads a sequence of bytes from a slave device (p167, 16.4.2 Programming the I2C controller for I2C Read, IMX6FG).

The return data buffer always matches the requested size, otherwise an error is returned.

The address length (`alen`) parameter should be set greater then 0 for ordinary I2C reads (`SLAVE W|ADDR|SLAVE R|DATA`), equal to 0 when not sending a register address (`SLAVE W|SLAVE R|DATA`) and less than 0 only to send a slave read (`SLAVE R|DATA`).

func (*I2C) Write 

func (hw *I2C) Write(buf []byte, slave uint8, addr uint32, alen int) (err error)

Write writes a sequence of bytes to a slave device (p170, 16.4.4 Programming the I2C controller for I2C Write, IMX6FG)

Set greater then 0 for ordinary I2C write (`SLAVE W|ADDR|DATA`), set equal then 0 to not send register address (`SLAVE W|DATA`), alen less then 0 is invalid.

The address length (`alen`) parameter should be set greater then 0 for ordinary I2C writes (`SLAVE W|ADDR|DATA`), equal to 0 when not sending a register address (`SLAVE W|DATA`), values less than 0 are not valid.

type Pad 

type Pad struct {
	// contains filtered or unexported fields
}

Pad instance.

func NewPad 

func NewPad(mux uint32, pad uint32, daisy uint32) (*Pad, error)

NewPad initializes a pad.

func (*Pad) Ctl 

func (pad *Pad) Ctl(ctl uint32)

Ctl configures the pad control register.

func (*Pad) Mode 

func (pad *Pad) Mode(mode uint32)

Mode configures the pad iomux mode.

func (*Pad) Select 

func (pad *Pad) Select(input uint32)

Select configures the pad daisy chain register.

func (*Pad) SoftwareInput 

func (pad *Pad) SoftwareInput(enabled bool)

SoftwareInput configures the pad SION bit.

type UART 

type UART struct {
	sync.Mutex

	// port speed
	Baudrate uint32
	// DTE mode
	DTE bool
	// hardware flow control
	Flow bool
	// contains filtered or unexported fields
}

UART represents a serial port instance

func (*UART) Disable 

func (hw *UART) Disable()

Disable disables the UART.

func (*UART) Enable 

func (hw *UART) Enable()

Enable enables the UART, this is only required after an explicit disable (see Disable()) as initialized interfaces (see Init()) are enabled by default.

func (*UART) Init 

func (hw *UART) Init()

Init initializes and enables the UART for RS-232 mode, p3605, 55.13.1 Programming the UART in RS-232 mode, IMX6ULLRM.

func (*UART) Read 

func (hw *UART) Read(buf []byte) (n int)

Read available data to buffer from serial port.

func (*UART) Rx 

func (hw *UART) Rx() (c byte, valid bool)

Rx receives a single character from the serial port.

func (*UART) Tx 

func (hw *UART) Tx(c byte)

Tx transmits a single character to the serial port.

func (*UART) Write 

func (hw *UART) Write(buf []byte)

Write data from buffer to serial port.

Source Files

View all Source files

Directories

Path Synopsis
Package csu implements a driver for the Central Security Unit (CSU) included in NXP i.MX6ULL/i.MX6ULZ SoCs.
 Package csu implements a driver for the Central Security Unit (CSU) included in NXP i.MX6ULL/i.MX6ULZ SoCs.
Package dcp implements a driver for the NXP Data Co-Processor (DCP), a cryptographic hardware accelerator included in i.MX6ULL/i.MX6ULZ SoCs.
 Package dcp implements a driver for the NXP Data Co-Processor (DCP), a cryptographic hardware accelerator included in i.MX6ULL/i.MX6ULZ SoCs.
Package imx6ul provides hardware initialization, automatically on import, for the i.MX6UL family of System-on-Chip components.
 Package imx6ul provides hardware initialization, automatically on import, for the i.MX6UL family of System-on-Chip components.
Package ocotp implements a driver for the NXP On-Chip OTP Controller (OCOTP_CTRL), included in i.MX6 series SoCs to interface with on-chip fuses, including write operation.
 Package ocotp implements a driver for the NXP On-Chip OTP Controller (OCOTP_CTRL), included in i.MX6 series SoCs to interface with on-chip fuses, including write operation.
Package rngb implements a driver for the NXP True Random Number Generator (RNGB) included in i.MX6ULL/i.MX6ULZ SoCs.
 Package rngb implements a driver for the NXP True Random Number Generator (RNGB) included in i.MX6ULL/i.MX6ULZ SoCs.
Package tzasc implements a driver for the TrustZone Address Space Controller (TZASC) included in NXP i.MX6ULL/i.MX6ULZ SoCs.
 Package tzasc implements a driver for the TrustZone Address Space Controller (TZASC) included in NXP i.MX6ULL/i.MX6ULZ SoCs.
Package usb implements a driver for the USB PHY designated as NXP USBOH3USBO2, included in i.MX6 SoCs.
 Package usb implements a driver for the USB PHY designated as NXP USBOH3USBO2, included in i.MX6 SoCs.
Package usdhc implements a driver for Freescale Enhanced Secure Digital Host Controller (eSDHC) interface, also known as NXP Ultra Secured Digital Host Controller (uSDHC).
 Package usdhc implements a driver for Freescale Enhanced Secure Digital Host Controller (eSDHC) interface, also known as NXP Ultra Secured Digital Host Controller (uSDHC).

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