core

package
Version: v0.0.0-...-9389419 Latest Latest
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Published: Jul 27, 2013 License: MIT Imports: 3 Imported by: 0

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Index

Constants

View Source
const (
	WORD_INSTR_MASK = 0xf800
	WORD_INSTR1     = 0xe800
	WORD_INSTR2     = 0xf000
	WORD_INSTR3     = 0xf800
)

If bits [15:11] of the instruction being decoded are any of * the following WORD_INSTR, then the instruction is the first * halfword of a 32-bit instruction. * ARMv7-M ARM A5.1

Variables

View Source
var ErrIncompleteInstruction = errors.New("Only first halfword of word instruction decoded.")
View Source
var ErrUndefinedInstruction = errors.New("Instruction not defined.")
View Source
var InstrOpcodes16 = map[Opcode]DecodeFunc{
	Opcode{mask: 0xf800, value: 0x0000}: LslImm16,
	Opcode{mask: 0xffc0, value: 0x4080}: LslReg16,
	Opcode{mask: 0xf800, value: 0x0800}: LsrImm16,
	Opcode{mask: 0xffc0, value: 0x40c0}: LsrReg16,
	Opcode{mask: 0xf800, value: 0x1000}: AsrImm16,
	Opcode{mask: 0xf800, value: 0x2000}: MovImm16,
	Opcode{mask: 0xff00, value: 0x4600}: MovReg16T1,
	Opcode{mask: 0xffc0, value: 0x0000}: MovReg16T2,
	Opcode{mask: 0xfe00, value: 0x1800}: AddReg16T1,
	Opcode{mask: 0xff00, value: 0x4400}: AddReg16T2,
	Opcode{mask: 0xff78, value: 0x4468}: AddRegSP16T1,
	Opcode{mask: 0xff87, value: 0x4485}: AddRegSP16T2,
	Opcode{mask: 0xfe00, value: 0x1a00}: SubReg16T1,
	Opcode{mask: 0xfe00, value: 0x1c00}: AddImm16T1,
	Opcode{mask: 0xf800, value: 0x3000}: AddImm16T2,
}
View Source
var InstrOpcodes32 = map[Opcode]DecodeFunc{}

Functions

func ASR

func ASR(regs *Registers, value uint32, shift_n uint8, setflags SetFlags) uint32

Perform ASR instruction, updating condition codes

func ASR_C

func ASR_C(value uint32, amount uint8) (uint32, bool)

Right shift value by a positive amount, copying the leftmost bit

func AddImmediate

func AddImmediate(regs *Registers, instr InstrFields)

Perform addition instruction (imm), updating condition codes

func AddRegister

func AddRegister(regs *Registers, instr InstrFields, shift Shift)

Perform addition instruction (reg), with shift, updating condition codes

func AddWithCarry

func AddWithCarry(x uint32, y uint32, carry_in uint8) (uint32, uint8, uint8)

Perform actual addition operation, determining carry out and overflow

func LSL

func LSL(regs *Registers, value uint32, shift_n uint8, setflags SetFlags) uint32

Perform LSL instruction, updating condition codes

func LSL_C

func LSL_C(value uint32, amount uint8) (uint32, bool)

Left shift value by a positive amount

func LSR

func LSR(regs *Registers, value uint32, shift_n uint8, setflags SetFlags) uint32

Perform LSR instruction, updating condition codes

func LSR_C

func LSR_C(value uint32, amount uint8) (uint32, bool)

Right shift value by a positive amount

func MoveRegister

func MoveRegister(regs *Registers, dest RegIndex, source RegIndex, setflags SetFlags, carry bool)

func MoveValue

func MoveValue(regs *Registers, dest RegIndex, value uint32, setflags SetFlags, carry bool)

Move value into destination register, updating condition codes

func ShiftOp

func ShiftOp(regs *Registers, value uint32, shift_n uint8, setflags SetFlags, do_shift ShiftFunc) uint32

Perform shift operation, updating condition codes

func SubRegister

func SubRegister(regs *Registers, instr InstrFields, shift Shift)

Perform subtraction instruction (reg), with shift, updating condition codes

Types

type AddImmT1

type AddImmT1 InstrFields

ADD (immediate) * ARM ARM A7.7.3 * Encoding T1

func (AddImmT1) Execute

func (instr AddImmT1) Execute(regs *Registers)

func (AddImmT1) String

func (instr AddImmT1) String() string

type AddImmT2

type AddImmT2 InstrFields

ADD (immediate) * ARM ARM A7.7.3 * Encoding T2

func (AddImmT2) Execute

func (instr AddImmT2) Execute(regs *Registers)

func (AddImmT2) String

func (instr AddImmT2) String() string

type AddRegSPT1

type AddRegSPT1 InstrFields

ADD (SP plus register) * ARM ARM A7.7.6 * Encoding T1

func (AddRegSPT1) Execute

func (instr AddRegSPT1) Execute(regs *Registers)

func (AddRegSPT1) String

func (instr AddRegSPT1) String() string

type AddRegSPT2

type AddRegSPT2 InstrFields

ADD (SP plus register) * ARM ARM A7.7.6 * Encoding T2

func (AddRegSPT2) Execute

func (instr AddRegSPT2) Execute(regs *Registers)

func (AddRegSPT2) String

func (instr AddRegSPT2) String() string

type AddRegT1

type AddRegT1 InstrFields

ADD (register) * ARM ARM A7.7.4 * Encoding T1

func (AddRegT1) Execute

func (instr AddRegT1) Execute(regs *Registers)

func (AddRegT1) String

func (instr AddRegT1) String() string

type AddRegT2

type AddRegT2 InstrFields

ADD (register) * ARM ARM A7.7.4 * Encoding T2

func (AddRegT2) Execute

func (instr AddRegT2) Execute(regs *Registers)

func (AddRegT2) String

func (instr AddRegT2) String() string

type Apsr

type Apsr struct {
	N  bool  // Negative
	Z  bool  // Zero
	C  bool  // Carry
	V  bool  // Overflow
	Q  bool  // Saturation
	GE uint8 // Greater than or equal flags
}

type AsrImm

type AsrImm InstrFields

ASR - Arithmetic Shift Right (immediate) * ARM ARM A7.7.10

func (AsrImm) Execute

func (instr AsrImm) Execute(regs *Registers)

func (AsrImm) String

func (instr AsrImm) String() string

type Control

type Control struct {
	Npriv bool   // NOT privilege
	Spsel SPType // SP select
	Fpca  bool   // FP extension enable
}

type DecodeFunc

type DecodeFunc func(FetchedInstr) DecodedInstr

type DecodedInstr

type DecodedInstr interface {
	Execute(*Registers)
}

func AddImm16T1

func AddImm16T1(instr FetchedInstr) DecodedInstr

func AddImm16T2

func AddImm16T2(instr FetchedInstr) DecodedInstr

func AddReg16T1

func AddReg16T1(instr FetchedInstr) DecodedInstr

func AddReg16T2

func AddReg16T2(instr FetchedInstr) DecodedInstr

func AddRegSP16T1

func AddRegSP16T1(instr FetchedInstr) DecodedInstr

func AddRegSP16T2

func AddRegSP16T2(instr FetchedInstr) DecodedInstr

func AsrImm16

func AsrImm16(instr FetchedInstr) DecodedInstr

func LslImm16

func LslImm16(instr FetchedInstr) DecodedInstr

func LslReg16

func LslReg16(instr FetchedInstr) DecodedInstr

func LsrImm16

func LsrImm16(instr FetchedInstr) DecodedInstr

func LsrReg16

func LsrReg16(instr FetchedInstr) DecodedInstr

func MovImm16

func MovImm16(instr FetchedInstr) DecodedInstr

func MovReg16T1

func MovReg16T1(instr FetchedInstr) DecodedInstr

func MovReg16T2

func MovReg16T2(instr FetchedInstr) DecodedInstr

func SubReg16T1

func SubReg16T1(instr FetchedInstr) DecodedInstr

type Epsr

type Epsr struct {
	T   bool   // Thumb bit
	ICI uint16 // Interrupt-continue
	IT  uint16 // IT block flags
}

type FetchedInstr

type FetchedInstr interface {
	Decode() (DecodedInstr, error)
	String() string
	Uint32() uint32
}

type FetchedInstr16

type FetchedInstr16 uint16

func (FetchedInstr16) Decode

func (instr FetchedInstr16) Decode() (DecodedInstr, error)

func (FetchedInstr16) Extend

func (upper FetchedInstr16) Extend(lower FetchedInstr16) FetchedInstr32

Extend upper halfword of instruction with lower halfword to make 32-bit instruction

func (FetchedInstr16) String

func (instr FetchedInstr16) String() string

func (FetchedInstr16) Uint32

func (instr FetchedInstr16) Uint32() uint32

type FetchedInstr32

type FetchedInstr32 uint32

func (FetchedInstr32) Decode

func (instr FetchedInstr32) Decode() (DecodedInstr, error)

func (FetchedInstr32) String

func (instr FetchedInstr32) String() string

func (FetchedInstr32) Uint32

func (instr FetchedInstr32) Uint32() uint32

type GeneralRegs

type GeneralRegs [13]uint32

type InstrFields

type InstrFields struct {
	Imm uint32
	Rd  RegIndex
	Rm  RegIndex
	Rn  RegIndex
	// contains filtered or unexported fields
}

type Ipsr

type Ipsr struct {
	ExcpNum uint16
}

type LslImm

type LslImm InstrFields

LSL - Logical Shift Left (immediate) * ARM ARM A7.7.67

func (LslImm) Execute

func (instr LslImm) Execute(regs *Registers)

func (LslImm) String

func (instr LslImm) String() string

type LslReg

type LslReg InstrFields

LSL - Logical Shift Left (register) * ARM ARM A7.7.68

func (LslReg) Execute

func (instr LslReg) Execute(regs *Registers)

func (LslReg) String

func (instr LslReg) String() string

type LsrImm

type LsrImm InstrFields

LSR - Logical Shift Right (immediate) * ARM ARM A7.7.69

func (LsrImm) Execute

func (instr LsrImm) Execute(regs *Registers)

func (LsrImm) String

func (instr LsrImm) String() string

type LsrReg

type LsrReg InstrFields

LSR - Logical Shift Right (register) * ARM ARM A7.7.70

func (LsrReg) Execute

func (instr LsrReg) Execute(regs *Registers)

func (LsrReg) String

func (instr LsrReg) String() string

type Mode

type Mode uint8
const (
	MODE_THREAD Mode = iota
	MODE_HANDLER
)

type MovImm

type MovImm InstrFields

MOV - Move (immediate) * ARM ARM A7.7.75

func (MovImm) Execute

func (instr MovImm) Execute(regs *Registers)

func (MovImm) String

func (instr MovImm) String() string

type MovRegT1

type MovRegT1 InstrFields

MOV - Move (register) * ARM ARM A7.7.76 * Encoding T1

func (MovRegT1) Execute

func (instr MovRegT1) Execute(regs *Registers)

func (MovRegT1) String

func (instr MovRegT1) String() string

type MovRegT2

type MovRegT2 InstrFields

MOV - Move (register) * ARM ARM A7.7.76 * Encoding T2

func (MovRegT2) Execute

func (instr MovRegT2) Execute(regs *Registers)

func (MovRegT2) String

func (instr MovRegT2) String() string

type Opcode

type Opcode struct {
	// contains filtered or unexported fields
}

func (*Opcode) Match

func (op *Opcode) Match(instr FetchedInstr) bool

type RegIndex

type RegIndex uint8
const (
	SP RegIndex = 13
	LR RegIndex = 14
	PC RegIndex = 15
)

Special registers in r13-15

func (RegIndex) String

func (i RegIndex) String() string

type Registers

type Registers struct {
	Apsr      Apsr
	Ipsr      Ipsr
	Epsr      Epsr
	Mode      Mode
	Primask   bool
	Faultmask bool
	Basepri   uint8
	Control   Control
	// contains filtered or unexported fields
}

func (*Registers) ALUWritePC

func (regs *Registers) ALUWritePC(addr uint32)

func (*Registers) BranchTo

func (regs *Registers) BranchTo(addr uint32)

func (*Registers) BranchWritePC

func (regs *Registers) BranchWritePC(addr uint32)

func (Registers) InITBlock

func (regs Registers) InITBlock() bool

func (Registers) LastInITBlock

func (regs Registers) LastInITBlock() bool

func (Registers) LookupSP

func (regs Registers) LookupSP() SPType

func (Registers) Lr

func (regs Registers) Lr() uint32

func (Registers) Msp

func (regs Registers) Msp() uint32

func (Registers) Pc

func (regs Registers) Pc() uint32

func (Registers) Pretty

func (regs Registers) Pretty() string

func (Registers) Print

func (regs Registers) Print()

func (Registers) Psp

func (regs Registers) Psp() uint32

func (Registers) R

func (regs Registers) R(i RegIndex) uint32

func (*Registers) SetR

func (regs *Registers) SetR(i RegIndex, value uint32)

func (Registers) Sp

func (regs Registers) Sp() uint32

type SPRegs

type SPRegs [2]uint32

type SPType

type SPType uint8
const (
	MSP SPType = 0
	PSP SPType = 1
)

type SetFlags

type SetFlags uint8
const (
	ALWAYS SetFlags = iota
	NEVER
	NOT_IT // Only set condition codes if not in IT block
)

func (SetFlags) ShouldSetFlags

func (setflags SetFlags) ShouldSetFlags(regs Registers) bool

func (SetFlags) String

func (setflags SetFlags) String() string

type Shift

type Shift struct {
	// contains filtered or unexported fields
}

func (Shift) Evaluate

func (shift Shift) Evaluate(input uint32) (uint32, bool)

type ShiftFunc

type ShiftFunc func(uint32, uint8) (uint32, bool)

Generic shifting function * * @param value uint32 Value to shift * @param amount uint8 Amount to shift by * * @return result uint32 Result of shift * @return carry bool Carry out of shift

type SubRegT1

type SubRegT1 InstrFields

SUB (register) * ARM ARM A7.7.172 * Encoding T1

func (SubRegT1) Execute

func (instr SubRegT1) Execute(regs *Registers)

func (SubRegT1) String

func (instr SubRegT1) String() string

type UndefinedInstr

type UndefinedInstr InstrFields

func (UndefinedInstr) Execute

func (instr UndefinedInstr) Execute(regs *Registers)

Placeholder UNDEFINED instruction

type UnpredictableInstr

type UnpredictableInstr InstrFields

func (UnpredictableInstr) Execute

func (instr UnpredictableInstr) Execute(regs *Registers)

Case to execute in the event of UNPREDICTABLE instruction behavior

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