arm

package module
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 Go to latest Published: Aug 21, 2022 License: MPL-2.0 Imports: 2 Imported by: 0

README

package arm

import "github.com/wdamron/arm"

Package arm implements an ARMv8 (AArch64) instruction assembler in Go, for runtime or ahead-of-time generation of executable code. SVE instructions are not yet supported.

This library is mostly adapted from the CensoredUsername/dynasm-rs (Rust) project, and is not heavily tested.

Brief Overview

The Assembler type encodes executable instructions to a code buffer.

Some instructions support label offset arguments, which may be resolved by the Assembler and encoded after all label addresses are assigned.

The following are argument types:

  • Reg: integer, SP, SIMD scalar, or SIMD vector register (with optional element index)
  • RegList: list of sequential registers
  • Ref: memory reference with register base, optionally followed by X register or immediate for post-indexing
  • RefOffset: memory reference with register base and immediate offset
  • RefPreIndexed: pre-indexed memory reference with register base and immediate offset
  • RefIndexed: memory index with register base, register index, and optional index modifier
  • Imm: 32-bit immediate integer
  • Float: 32-bit immediate float
  • Wide: 64-bit immediate integer
  • Mod: modifier with optional immediate shift/rotate
  • Label: label reference with optional offset from label address
  • Symbol: constant identifier

Additional References

Documentation

Overview

Package asm implements an ARMv8 (AArch64) instruction assembler in Go.

This library is mostly adapted from the CensoredUsername/dynasm-rs (Rust) project, and is not heavily tested. See https://github.com/CensoredUsername/dynasm-rs. SVE instructions are not yet supported.

The Assembler type encodes executable instructions to a code buffer.

Some instructions support label offset arguments, which may be resolved by the Assembler and encoded after all label addresses are assigned.

The following are argument types:

  • Reg: integer, SP, SIMD scalar, or SIMD vector register (with optional element index)
  • RegList: list of sequential registers
  • Ref: memory reference with register base, optionally followed by X register or immediate for post-indexing
  • RefOffset: memory reference with register base and immediate offset
  • RefPreIndexed: pre-indexed memory reference with register base and immediate offset
  • RefIndexed: memory index with register base, register index, and optional index modifier
  • Imm: 32-bit immediate integer
  • Float: 32-bit immediate float
  • Wide: 64-bit immediate integer
  • Mod: modifier with optional immediate shift/rotate
  • Label: label reference with optional offset from label address
  • Symbol: constant identifier

Index

Constants

View Source 
const (
	CmdR0    uint8 // R0, encode a register or reference base into a 5-bit bitfield at bit 0
	CmdR5          // R5, encode a register or reference base into a 5-bit bitfield at bit 5
	CmdR10         // R10, encode a register or reference base into a 5-bit bitfield at bit 10
	CmdR16         // R16, encode a register or reference base into a 5-bit bitfield at bit 16
	CmdRLo16       // RLo16, encode a register in the range 0-15 into a 4-bit bitfield at bit 16
	CmdRNz16       // RNz16, encode a register (except 31) or reference base into a 5-bit bitfield at bit 16
	CmdREven       // REven(offset), encode an even register or reference base into a 5-bit bitfield at bit $0
	CmdRNext       // encode that this register should be the previous register, plus one

	CmdRwidth30 // Rwidth, SIMD 128-bit indicator at bit 30

	CmdUbits     // Ubits(offset, bitlen), encode an unsigned immediate starting at bit $0, $1 bits long
	CmdUscaled   // Uscaled(offset, bitlen, shift), encode an unsigned immediate, starting at bit $0, $1 bits long, shifted $2 bits to the right before encoding
	CmdUAlt2     // UAlt2(offset, *[2]uint8), encode an immediate that can only be a limited amount of options
	CmdUAlt4     // UAlt4(offset, *[4]uint8), encode an immediate that can only be a limited amount of options
	CmdUrange    // Urange(offset, min, max), (loc, min, max) asserts the immediate is below or equal to max, encodes the value of (imm-min)
	CmdUsub      // Usub(offset, bitlen, val), encode at $0, $1 bits long, $2 - value. Checks if the value is in the range 0 .. value
	CmdUnegmod   // Unegmod(offset, bitlen), encode at $0, $1 bits long, -value % (1 << $1). Checks if the value is in the range 0 .. value
	CmdUsumdec   // Usumdec(offset, bitlen), encode at $0, $1 bits long, the value of the previous arg + the value of the current arg - 1
	CmdUfields11 // Ufields11(count), encode an immediate bitwise with $0 fields, into bits [11, 21, 20]
	CmdUfields30 // Ufields30(count), encode an immediate bitwise with $0 fields, into bits [30, 12, 11, 10]
	CmdUfields21 // Ufields21, encode an immediate bitwise with 1 field, into bit 21

	CmdSbits   // Sbits, encode a signed immediate starting at bit 12, 9 bits long
	CmdSscaled // Sscaled(shift), encode a signed immediate, starting at bit 15, 7 bits long, shifted $0 bits to the right before encoding

	CmdChkUbits   // ChkUbits(bitlen), checks if the pointed value fits in $0 (0, 6, 8)
	CmdChkUsum    // ChkUsum(shift), checks that the pointed value fits between 1 and (1 << $0) - prev
	CmdChkSscaled // ChkSscaled, with (offset 10, shift 3)
	CmdChkUrange1 // ChkUrange(max), // check if the pointed value is between 1 and $0
	CmdUslice     // Uslice(offset, bitlen, startoffset), encode at $0, $1 bits long, the bitslice starting at $2 from the current arg
	CmdSslice     // Sslice(offset, bitlen, startoffset), encodes at $0, $1 bits long, the bitslice starting at $2 from the current arg

	CmdSpecial // Special(offset, SpecialType)

	CmdRotates  // Rotates, 2-bits field encoding at bit 22 [LSL, LSR, ASR, ROR]
	CmdExtendsW // ExtendsW, 3-bits field encoding at bit 13 [UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX]. Additionally, LSL is interpreted as UXTW
	CmdExtendsX // ExtendsX, 3-bits field encoding at bit 13 [UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX]. Additionally, LSL is interpreted as UXTX

	CmdCond    // Cond(offset), normal condition code 4-bit encoding
	CmdCondInv // CondInv(offset), 4-bit encoding, but the last bit is inverted. No AL/NV allowed

	CmdLitList // LitList(offset, *[]Symbol)

	CmdOffset // Offset(RelType)

	CmdAdv  // advances the argument pointer, only needed to skip over an argument.
	CmdBack // moves the argument pointer back.

	RelB     // b, bl 26 bits, dword aligned
	RelBCond // b.cond, cbnz, cbz, ldr, ldrsw, prfm: 19 bits, dword aligned
	RelAdr   // adr split 21 bit, byte aligned
	RelAdrp  // adrp split 21 bit, 4096-byte aligned
	RelTbz   // tbnz, tbz: 14 bits, dword aligned

	SymATOPS
	SymDCOPS
	SymICOPS
	SymTLBIOPS
	SymBARRIEROPS
	SymMSRIMMOPS
	SymCONTROLREGS
)
View Source 
const (
	SpecialImmWideInv32 uint8
	SpecialImmWideInv64
	SpecialImmWide32
	SpecialImmWide64
	SpecialImmStretched
	SpecialImmLogical32
	SpecialImmLogical64
	SpecialImmFloat
	SpecialImmFloatSplit
)

Special immediate types (CmdSpecial)

View Source 
const (
	MatLitSymbol uint8 // Lit(Symbol)
	MatLitInt          // LitInt(int32), immediate literal
	MatLitFloat        // LitFloat(float32), float literal
	MatSymbol          // Symbol
	MatCond            // condition code Symbol
	MatImm             // 32/64-bit integer immediate
	MatFloat           // 32-bit float immediate (FMOV)

	MatW // scalar 32-bit integer register (except WSP)
	MatX // scalar 64-bit integer register (except XSP)

	MatWSP // 32-bit stack pointer register
	MatXSP // 64-bit stack pointer register

	MatB // scalar simd 8-bit register
	MatH // scalar simd 16-bit register
	MatS // scalar simd 32-bit register
	MatD // scalar simd 64-bit register
	MatQ // scalar simd 128-bit register

	MatV              // V(Size), vector register with elements of the specified size. Accepts a lane count of either 64 or 128 total bits
	MatVStatic        // VStatic(Size, lanes), vector register with elements of the specifized size, with the specified lane count
	MatVElement       // VElement(Size), vector register with element specifier, with the element of the specified size. The lane count is unchecked.
	MatVElementStatic // VElementStatic(Size, idx), vector register with element specifier, with the element of the specified size and the element index set to the provided value
	MatVStaticElement // VStaticElement(Size, lanes), vector register with elements of the specified size, with the specified lane count, with an element specifier

	MatRegList        // RegList(len, Size), register list with $0 items, with the elements of size $1
	MatRegListStatic  // RegListStatic(len, Size, lanes), register list with $0 items, with the elements of size $1 and a lane count of $2
	MatRegListElement // RegListElement(len, Size), register list with element specifier. It has $0 items with a size of $1

	MatOffset // jump offset

	MatRefBase   // memory reference with base register (integer or SP register), optionally followed by a register or immediate offset argument for post-indexing
	MatRefOffset // memory reference with base register (integer or SP register) and immediate offset
	MatRefPre    // pre-indexed memory reference with base register (integer or SP register) and immediate offset
	MatRefIndex  // memory reference with base register (integer or SP register), index register (integer register), and optional index modifier

	MatLitMod // LitMod(Mod), a single modifier
	MatMod    // Mod(*[]Mod), a set of allowed modifiers

	MatEnd // possible op mnemnonic end (everything after this point uses the default encoding)
)
View Source 
const (
	SymLSL uint8
	SymLSR
	SymASR
	SymROR
	SymMSL
	SymSXTX
	SymSXTW
	SymSXTH
	SymSXTB
	SymUXTX
	SymUXTW
	SymUXTH
	SymUXTB
)

Modifier identifiers

View Source 
const (
	SymExtends uint8
	SymExtendsW
	SymExtendsX
	SymShifts
	SymRotates
)

Modifier lists

Variables

View Source 
var (
	ModSXTX = Mod{ID: SymSXTX} // ModSXTX is an extension modifier argument with ID SymSXTX
	ModSXTW = Mod{ID: SymSXTW} // ModSXTW is an extension modifier argument with ID SymSXTW
	ModSXTH = Mod{ID: SymSXTH} // ModSXTH is an extension modifier argument with ID SymSXTH
	ModSXTB = Mod{ID: SymSXTB} // ModSXTB is an extension modifier argument with ID SymSXTB
	ModUXTX = Mod{ID: SymUXTX} // ModUXTX is an extension modifier argument with ID SymUXTX
	ModUXTW = Mod{ID: SymUXTW} // ModUXTW is an extension modifier argument with ID SymUXTW
	ModUXTH = Mod{ID: SymUXTH} // ModUXTH is an extension modifier argument with ID SymUXTH
	ModUXTB = Mod{ID: SymUXTB} // ModUXTB is an extension modifier argument with ID SymUXTB

	ModLSL = Mod{ID: SymLSL} // ModLSL is a shift modifier argument with ID SymLSL
	ModLSR = Mod{ID: SymLSR} // ModLSR is a shift modifier argument with ID SymLSR
	ModASR = Mod{ID: SymASR} // ModASR is a shift modifier argument with ID SymASR
	ModROR = Mod{ID: SymROR} // ModROR is a rotate modifier argument with ID SymROR
	ModMSL = Mod{ID: SymMSL} // ModMSL is a shift modifier argument with ID SymMSL
)

Modifiers

View Source 
var (
	WZR = Reg{ID: 31, Type: RW} // 32-bit zero register
	XZR = Reg{ID: 31, Type: RX} // 64-bit zero register

	WSP = Reg{ID: 31, Type: RWSP} // 32-bit stack pointer register
	XSP = Reg{ID: 31, Type: RXSP} // 64-bit stack pointer register
)
View Source 
var ATOPS = [...]Symbol{S1E1R, S1E1W, S1E0R, S1E0W, S1E2R, S1E2W, S12E1R, S12E1W, S12E0R, S12E0W, S1E3R, S1E3W, S1E1RP, S1E1WP}

Address Translation

View Source 
var Alts2 = [...][2]uint16{
	{0, 0},
	{0, 1},
	{0, 2},
	{0, 3},
	{0, 4},
	{0, 8},
	{0, 12},
	{0, 16},
	{8, 16},
	{90, 270},
}
View Source 
var Alts4 = [...][4]uint16{
	{0, 8, 16, 24},
	{0, 16, 32, 48},
	{0, 90, 180, 270},
}
View Source 
var BARRIEROPS = [...]Symbol{SY, ST, LD, ISH, ISHST, ISHLD, NSH, NSHST, NSHLD, OSH, OSHST, OSHLD}

Instruction/Data Synchronization Barriers

View Source 
var CmdArgCounts = [...]uint8{
	CmdR0:         0,
	CmdR5:         0,
	CmdR10:        0,
	CmdR16:        0,
	CmdRLo16:      0,
	CmdRNz16:      0,
	CmdREven:      1,
	CmdRNext:      0,
	CmdRwidth30:   0,
	CmdUbits:      2,
	CmdUscaled:    3,
	CmdUAlt2:      2,
	CmdUAlt4:      2,
	CmdUrange:     3,
	CmdUsub:       3,
	CmdUnegmod:    2,
	CmdUsumdec:    2,
	CmdUfields11:  1,
	CmdUfields30:  1,
	CmdUfields21:  0,
	CmdSbits:      0,
	CmdSscaled:    1,
	CmdChkUbits:   1,
	CmdChkUsum:    1,
	CmdChkSscaled: 0,
	CmdChkUrange1: 1,
	CmdUslice:     3,
	CmdSslice:     3,
	CmdSpecial:    2,
	CmdRotates:    0,
	CmdExtendsW:   0,
	CmdExtendsX:   0,
	CmdCond:       1,
	CmdCondInv:    1,
	CmdLitList:    2,
	CmdOffset:     1,
	CmdAdv:        0,
	CmdBack:       0,
}
View Source 
var CmdName = [...]string{
	CmdR0:          "CmdR0",
	CmdR5:          "CmdR5",
	CmdR10:         "CmdR10",
	CmdR16:         "CmdR16",
	CmdRLo16:       "CmdRLo16",
	CmdRNz16:       "CmdRNz16",
	CmdREven:       "CmdREven",
	CmdRNext:       "CmdRNext",
	CmdRwidth30:    "CmdRwidth30",
	CmdUbits:       "CmdUbits",
	CmdUscaled:     "CmdUscaled",
	CmdUAlt2:       "CmdUAlt2",
	CmdUAlt4:       "CmdUAlt4",
	CmdUrange:      "CmdUrange",
	CmdUsub:        "CmdUsub",
	CmdUnegmod:     "CmdUnegmod",
	CmdUsumdec:     "CmdUsumdec",
	CmdUfields11:   "CmdUfields11",
	CmdUfields30:   "CmdUfields30",
	CmdUfields21:   "CmdUfields21",
	CmdSbits:       "CmdSbits",
	CmdSscaled:     "CmdSscaled",
	CmdChkUbits:    "CmdChkUbits",
	CmdChkUsum:     "CmdChkUsum",
	CmdChkSscaled:  "CmdChkSscaled",
	CmdChkUrange1:  "CmdChkUrange1",
	CmdUslice:      "CmdUslice",
	CmdSslice:      "CmdSslice",
	CmdSpecial:     "CmdSpecial",
	CmdRotates:     "CmdRotates",
	CmdExtendsW:    "CmdExtendsW",
	CmdExtendsX:    "CmdExtendsX",
	CmdCond:        "CmdCond",
	CmdCondInv:     "CmdCondInv",
	CmdLitList:     "CmdLitList",
	CmdOffset:      "CmdOffset",
	CmdAdv:         "CmdAdv",
	CmdBack:        "CmdBack",
	RelB:           "RelB",
	RelBCond:       "RelBCond",
	RelAdr:         "RelAdr",
	RelAdrp:        "RelAdrp",
	RelTbz:         "RelTbz",
	SymATOPS:       "SymATOPS",
	SymDCOPS:       "SymDCOPS",
	SymICOPS:       "SymICOPS",
	SymTLBIOPS:     "SymTLBIOPS",
	SymBARRIEROPS:  "SymBARRIEROPS",
	SymMSRIMMOPS:   "SymMSRIMMOPS",
	SymCONTROLREGS: "SymCONTROLREGS",
}
View Source 
var Commands = [...]byte{}/* 23065 elements not displayed */

The Commands table contains opcode/encoding info for all instructions. Each encoding contains a 32-bit opcode, followed by a length-prefixed list of encoding operators. Encoding operators apply to Flat types. Opcode bytes are big-endian ordered to match encoding diagrams. The table is indexed through offsets stored in the Patterns table.

View Source 
var DCOPS = [...]Symbol{IVAC, ISW, CSW, CISW, ZVA, CVAC, CVAU, CIVAC, CVAP}

Data Cache

View Source 
var ICOPS = [...]Symbol{IALLUIS, IALLU}

Instruction Cache

View Source 
var MSRIMMOPS = [...]Symbol{SPSEL, DAIFSET, DAIFCLR, UAO, PAN, DIT}

System Registers

View Source 
var MatchName = [...]string{
	MatLitSymbol:      "MatLitSymbol",
	MatLitInt:         "MatLitInt",
	MatLitFloat:       "MatLitFloat",
	MatSymbol:         "MatSymbol",
	MatCond:           "MatCond",
	MatImm:            "MatImm",
	MatFloat:          "MatFloat",
	MatW:              "MatW",
	MatX:              "MatX",
	MatWSP:            "MatWSP",
	MatXSP:            "MatXSP",
	MatB:              "MatB",
	MatH:              "MatH",
	MatS:              "MatS",
	MatD:              "MatD",
	MatQ:              "MatQ",
	MatV:              "MatV",
	MatVStatic:        "MatVStatic",
	MatVElement:       "MatVElement",
	MatVElementStatic: "MatVElementStatic",
	MatVStaticElement: "MatVStaticElement",
	MatRegList:        "MatRegList",
	MatRegListStatic:  "MatRegListStatic",
	MatRegListElement: "MatRegListElement",
	MatOffset:         "MatOffset",
	MatRefBase:        "MatRefBase",
	MatRefOffset:      "MatRefOffset",
	MatRefPre:         "MatRefPre",
	MatRefIndex:       "MatRefIndex",
	MatLitMod:         "MatLitMod",
	MatMod:            "MatMod",
	MatEnd:            "MatEnd",
}
View Source 
var MatcherArgCounts = [...]uint8{
	MatLitSymbol:      1,
	MatLitInt:         1,
	MatLitFloat:       1,
	MatSymbol:         0,
	MatCond:           0,
	MatImm:            0,
	MatFloat:          0,
	MatW:              0,
	MatX:              0,
	MatWSP:            0,
	MatXSP:            0,
	MatB:              0,
	MatH:              0,
	MatS:              0,
	MatD:              0,
	MatQ:              0,
	MatV:              1,
	MatVStatic:        2,
	MatVElement:       1,
	MatVElementStatic: 2,
	MatVStaticElement: 2,
	MatRegList:        2,
	MatRegListStatic:  3,
	MatRegListElement: 2,
	MatOffset:         0,
	MatRefBase:        0,
	MatRefOffset:      0,
	MatRefPre:         0,
	MatRefIndex:       0,
	MatLitMod:         1,
	MatMod:            1,
	MatEnd:            0,
}
View Source 
var MatcherFlatArgCounts = [...]uint8{
	MatLitSymbol:      0,
	MatLitInt:         0,
	MatLitFloat:       0,
	MatSymbol:         1,
	MatCond:           1,
	MatImm:            1,
	MatFloat:          1,
	MatW:              1,
	MatX:              1,
	MatWSP:            1,
	MatXSP:            1,
	MatB:              1,
	MatH:              1,
	MatS:              1,
	MatD:              1,
	MatQ:              1,
	MatV:              1,
	MatVStatic:        1,
	MatVElement:       2,
	MatVElementStatic: 1,
	MatVStaticElement: 2,
	MatRegList:        1,
	MatRegListStatic:  1,
	MatRegListElement: 2,
	MatOffset:         1,
	MatRefBase:        1,
	MatRefOffset:      2,
	MatRefPre:         2,
	MatRefIndex:       4,
	MatLitMod:         1,
	MatMod:            2,
	MatEnd:            0,
}
View Source 
var ModList = [...][]uint8{
	SymExtends:  {SymUXTB, SymUXTH, SymUXTW, SymUXTX, SymSXTB, SymSXTH, SymSXTW, SymSXTX, SymLSL},
	SymExtendsW: {SymUXTB, SymUXTH, SymUXTW, SymSXTB, SymSXTH, SymSXTW},
	SymExtendsX: {SymUXTX, SymSXTX, SymLSL},
	SymShifts:   {SymLSL, SymLSR, SymASR},
	SymRotates:  {SymLSL, SymLSR, SymASR, SymROR},
}

ModList contains grouped modifier symbols.

View Source 
var ModListName = [...]string{
	SymExtends:  "SymExtends",
	SymExtendsW: "SymExtendsW",
	SymExtendsX: "SymExtendsX",
	SymShifts:   "SymShifts",
	SymRotates:  "SymRotates",
}
View Source 
var ModName = [...]string{
	SymLSL:  "SymLSL",
	SymLSR:  "SymLSR",
	SymASR:  "SymASR",
	SymROR:  "SymROR",
	SymSXTX: "SymSXTX",
	SymSXTW: "SymSXTW",
	SymSXTH: "SymSXTH",
	SymSXTB: "SymSXTB",
	SymUXTX: "SymUXTX",
	SymUXTW: "SymUXTW",
	SymUXTH: "SymUXTH",
	SymUXTB: "SymUXTB",
	SymMSL:  "SymMSL",
}
View Source 
var ModRequiresImm = [...]bool{
	SymLSL: true,
	SymLSR: true,
	SymASR: true,
	SymROR: true,
	SymMSL: true,
}
View Source 
var Patterns = [...]byte{}/* 20489 elements not displayed */

The Patterns table contains matching info for all instruction encodings. Each instruction's list of encodings is prefixed with the encoding count, followed by a length-prefixed list of matching operators and commands offset for each encoding; the commands offset is a 16-bit index into the Commands table. Matching operators apply to unflattened Arg types.

View Source 
var SizeName = [...]string{BYTE: "BYTE", WORD: "WORD", DWORD: "DWORD", QWORD: "QWORD", OWORD: "OWORD"}
View Source 
var SpecialName = [...]string{
	SpecialImmWideInv32:  "SpecialImmWideInv32",
	SpecialImmWideInv64:  "SpecialImmWideInv64",
	SpecialImmWide32:     "SpecialImmWide32",
	SpecialImmWide64:     "SpecialImmWide64",
	SpecialImmStretched:  "SpecialImmStretched",
	SpecialImmLogical32:  "SpecialImmLogical32",
	SpecialImmLogical64:  "SpecialImmLogical64",
	SpecialImmFloat:      "SpecialImmFloat",
	SpecialImmFloatSplit: "SpecialImmFloatSplit",
}
View Source 
var SymbolName = [...]string{}/* 142 elements not displayed */
View Source 
var SymbolValue = [...]uint16{}/* 142 elements not displayed */
View Source 
var TLBIOPS = [...]Symbol{VMALLE1IS, VAE1IS, ASIDE1IS, VAAE1IS, VALE1IS, VAALE1IS, VMALLE1, VAE1, ASIDE1, VAAE1, VALE1, VAALE1, IPAS2E1IS, IPAS2LE1IS, ALLE2IS, VAE2IS, ALLE1IS, VALE2IS, VMALLS12E1IS, IPAS2E1, IPAS2LE1, ALLE2, VAE2, ALLE1, VALE2, VMALLS12E1, ALLE3IS, VAE3IS, VALE3IS, ALLE3, VAE3, VALE3, VMALLE1OS, VAE1OS, ASIDE1OS, VAAE1OS, VALE1OS, VAALE1OS, RVAE1IS, RVAAE1IS, RVALE1IS, RVAALE1IS, RVAE1OS, RVAAE1OS, RVALE1OS, RVAALE1OS, RVAE1, RVAAE1, RVALE1, RVAALE1, RIPAS2E1IS, RIPAS2LE1IS, ALLE2OS, VAE2OS, ALLE1OS, VALE2OS, VMALLS12E1OS, RVAE2IS, RVALE2IS, IPAS2E1OS, RIPAS2E1, RIPAS2E1OS, IPAS2LE1OS, RIPAS2LE1, RIPAS2LE1OS, RVAE2OS, RVALE2OS, RVAE2, RVALE2, ALLE3OS, VAE3OS, VALE3OS, RVAE3IS, RVALE3IS, RVAE3OS, RVALE3OS, RVAE3, RVALE3}

Translation Table

Functions

This section is empty.

Types

type Arg 

type Arg interface {
	// contains filtered or unexported methods
}

Arg is any instruction argument.

The following are argument types:

  • Reg: integer, SP, SIMD scalar, or SIMD vector register (with optional element index)
  • RegList: list of sequential registers
  • Ref: memory reference with register base, optionally followed by X register or immediate for post-indexing
  • RefOffset: memory reference with register base and immediate offset
  • RefPreIndexed: pre-indexed memory reference with register base and immediate offset
  • RefIndexed: memory index with register base, register index, and optional index modifier
  • Imm: 32-bit immediate integer
  • Float: 32-bit immediate float
  • Wide: 64-bit immediate integer
  • Mod: modifier with optional immediate shift/rotate
  • Label: label reference with optional offset from label address
  • Symbol: constant identifier

type Assembler 

type Assembler struct {
	Code    []byte   // code buffer indexed by PC
	LabelPC []uint32 // label PC by ID
	Relocs  []Reloc  // label references
	Args    []Arg    // arguments for the current instruction
	Flat    []Flat   // flattened arguments for the current matched instruction
	PC      uint32   // current code offset

	CurrentInst Inst   // current instruction mnemonic, offset into the Patterns array
	Count       uint8  // available encodings for the current instruction
	Idx         int8   // encoding index for the current instruction
	SimdSize    uint8  // SIMD width for the current instruction when applicable
	Opcode      uint32 // opcode (without arguments) for the current matched instruction
	Err         error  // most recent error
	// contains filtered or unexported fields
}

Assembler encodes executable instructions to a code buffer.

Some instructions support Label offset arguments, which may be resolved and encoded after all label addresses are assigned.

func (*Assembler) ApplyRelocations 

func (a *Assembler) ApplyRelocations() bool

ApplyRelocations patches all instructions containing label offset arguments, with the currently assigned PC value for each label.

func (*Assembler) Commands 

func (a *Assembler) Commands() []EncOp

Commands returns the list of encoding operators for the most recent matching iteration, useful for debugging.

func (*Assembler) Init 

func (a *Assembler) Init(mem []byte)

Initialize or re-initialize the assembler with a new code buffer, resetting the PC and all state.

func (*Assembler) Inst 

func (a *Assembler) Inst(inst Inst, args ...Arg) bool

Inst advances to the first matched encoding for inst and args, then writes the matched instruction to the code buffer if one was found.

If no matching instruction was found or arguments could not be encoded, the call will return false and the Err field will be set.

func (*Assembler) NewLabel 

func (a *Assembler) NewLabel() Label

NewLabel registers a new label identifier at the current PC. The label may be used as an offset argument, and the PC for the label may be reassigned by calling SetLabel at the target PC. Label offset arguments must be processed through ApplyRelocations once all labels can be resolved.

func (*Assembler) Pattern 

func (a *Assembler) Pattern() []EncOp

Pattern returns the list of matching operators for the most recent matching iteration, useful for debugging.

func (*Assembler) SetLabel 

func (a *Assembler) SetLabel(label Label)

SetLabel sets the PC for a label to the current PC.

type EncOp 

type EncOp struct {
	Op uint8
	X  [3]uint8
}

EncOp is a matching or encoding operator decoded from the Patterns or Commands arrays. Operators are used internally, and exposed for debugging.

type ErrorMessage 

type ErrorMessage string

ErrorMessage is an error message type, returned when instruction matching or encoding fails. 

const (
	ErrInvalidInst     ErrorMessage = "invalid instruction id"
	ErrNoMatch         ErrorMessage = "no matching encoding"
	ErrInvalidEncoding ErrorMessage = "invalid instruction encoding"
)

func (ErrorMessage) Error 

func (err ErrorMessage) Error() string

type Flat 

type Flat interface {
	// contains filtered or unexported methods
}

Flat is an internal argument, flattened for encoding.

type FlatDefault 

type FlatDefault struct{}

FlatDefault is an internal default argument, flattened for encoding.

type FlatImm 

type FlatImm uint64

FlatImm is an internal immediate argument, flattened for encoding.

type FlatLabel 

type FlatLabel Label

FlatLabel is an internal label argument, flattened for encoding.

type FlatMod 

type FlatMod uint8

FlatMod is an internal modifier argument, flattened for encoding.

type FlatReg 

type FlatReg uint8

FlatReg is an internal register argument, flattened for encoding.

type Float 

type Float float32

Float is a 32-bit float immediate argument.

type Imm 

type Imm int32

Imm is a 32-bit integer immediate argument.

type Inst 

type Inst uint16

Inst is an instruction mnemonic. The integer value is an offset into the Patterns array. 

const (
	ABS       Inst = 1
	ADC       Inst = 37
	ADCS      Inst = 50
	ADD       Inst = 63
	ADDHN     Inst = 172
	ADDHN2    Inst = 209
	ADDP      Inst = 246
	ADDS      Inst = 293
	ADDV      Inst = 357
	ADR       Inst = 377
	ADRP      Inst = 383
	AESD      Inst = 389
	AESE      Inst = 399
	AESIMC    Inst = 409
	AESMC     Inst = 419
	AND       Inst = 429
	ANDS      Inst = 469
	ASR       Inst = 500
	ASRV      Inst = 525
	AT        Inst = 538
	AUTDA     Inst = 544
	AUTDB     Inst = 550
	AUTDZA    Inst = 556
	AUTDZB    Inst = 561
	AUTIA     Inst = 566
	AUTIA1716 Inst = 572
	AUTIASP   Inst = 576
	AUTIAZ    Inst = 580
	AUTIB     Inst = 584
	AUTIB1716 Inst = 590
	AUTIBSP   Inst = 594
	AUTIBZ    Inst = 598
	AUTIZA    Inst = 602
	AUTIZB    Inst = 607
	B         Inst = 612
	BCAX      Inst = 622
	BFC       Inst = 638
	BFI       Inst = 651
	BFM       Inst = 666
	BFXIL     Inst = 681
	BIC       Inst = 696
	BICS      Inst = 742
	BIF       Inst = 761
	BIT       Inst = 771
	BL        Inst = 781
	BLR       Inst = 786
	BLRAA     Inst = 791
	BLRAAZ    Inst = 797
	BLRAB     Inst = 802
	BLRABZ    Inst = 808
	BR        Inst = 813
	BRAA      Inst = 818
	BRAAZ     Inst = 824
	BRAB      Inst = 829
	BRABZ     Inst = 835
	BRK       Inst = 840
	BSL       Inst = 845
	CAS       Inst = 855
	CASA      Inst = 868
	CASAB     Inst = 881
	CASAH     Inst = 888
	CASAL     Inst = 895
	CASALB    Inst = 908
	CASALH    Inst = 915
	CASB      Inst = 922
	CASH      Inst = 929
	CASL      Inst = 936
	CASLB     Inst = 949
	CASLH     Inst = 956
	CASP      Inst = 963
	CASPA     Inst = 980
	CASPAL    Inst = 997
	CASPL     Inst = 1014
	CBNZ      Inst = 1031
	CBZ       Inst = 1042
	CCMN      Inst = 1053
	CCMP      Inst = 1082
	CFINV     Inst = 1111
	CFP       Inst = 1115
	CINC      Inst = 1122
	CINV      Inst = 1135
	CLREX     Inst = 1148
	CLS       Inst = 1156
	CLZ       Inst = 1188
	CMEQ      Inst = 1220
	CMGE      Inst = 1311
	CMGT      Inst = 1402
	CMHI      Inst = 1493
	CMHS      Inst = 1539
	CMLE      Inst = 1585
	CMLT      Inst = 1631
	CMN       Inst = 1677
	CMP       Inst = 1733
	CMTST     Inst = 1789
	CNEG      Inst = 1835
	CNT       Inst = 1848
	CPP       Inst = 1856
	CRC32B    Inst = 1863
	CRC32CB   Inst = 1870
	CRC32CH   Inst = 1877
	CRC32CW   Inst = 1884
	CRC32CX   Inst = 1891
	CRC32H    Inst = 1898
	CRC32W    Inst = 1905
	CRC32X    Inst = 1912
	CSDB      Inst = 1919
	CSEL      Inst = 1923
	CSET      Inst = 1938
	CSETM     Inst = 1949
	CSINC     Inst = 1960
	CSINV     Inst = 1975
	CSNEG     Inst = 1990
	DC        Inst = 2005
	DCPS1     Inst = 2011
	DCPS2     Inst = 2017
	DCPS3     Inst = 2023
	DMB       Inst = 2029
	DRPS      Inst = 2038
	DSB       Inst = 2042
	DUP       Inst = 2051
	DVP       Inst = 2130
	EON       Inst = 2137
	EOR       Inst = 2156
	EOR3      Inst = 2196
	ERET      Inst = 2212
	ERETAA    Inst = 2216
	ERETAB    Inst = 2220
	ESB       Inst = 2224
	EXT       Inst = 2228
	EXTR      Inst = 2255
	FABD      Inst = 2270
	FABS      Inst = 2319
	FACGE     Inst = 2358
	FACGT     Inst = 2407
	FADD      Inst = 2456
	FADDP     Inst = 2505
	FCADD     Inst = 2557
	FCCMP     Inst = 2591
	FCCMPE    Inst = 2613
	FCMEQ     Inst = 2635
	FCMGE     Inst = 2734
	FCMGT     Inst = 2833
	FCMLA     Inst = 2932
	FCMLE     Inst = 3002
	FCMLT     Inst = 3053
	FCMP      Inst = 3104
	FCMPE     Inst = 3138
	FCSEL     Inst = 3172
	FCVT      Inst = 3194
	FCVTAS    Inst = 3225
	FCVTAU    Inst = 3294
	FCVTL     Inst = 3363
	FCVTL2    Inst = 3382
	FCVTMS    Inst = 3401
	FCVTMU    Inst = 3470
	FCVTN     Inst = 3539
	FCVTN2    Inst = 3549
	FCVTNS    Inst = 3559
	FCVTNU    Inst = 3628
	FCVTPS    Inst = 3697
	FCVTPU    Inst = 3766
	FCVTXN    Inst = 3835
	FCVTXN2   Inst = 3850
	FCVTZS    Inst = 3860
	FCVTZU    Inst = 4009
	FDIV      Inst = 4158
	FJCVTZS   Inst = 4207
	FMADD     Inst = 4213
	FMAX      Inst = 4235
	FMAXNM    Inst = 4284
	FMAXNMP   Inst = 4333
	FMAXNMV   Inst = 4385
	FMAXP     Inst = 4399
	FMAXV     Inst = 4451
	FMIN      Inst = 4465
	FMINNM    Inst = 4514
	FMINNMP   Inst = 4563
	FMINNMV   Inst = 4615
	FMINP     Inst = 4629
	FMINV     Inst = 4681
	FMLA      Inst = 4695
	FMLAL     Inst = 4776
	FMLAL2    Inst = 4823
	FMLS      Inst = 4870
	FMLSL     Inst = 4951
	FMLSL2    Inst = 4998
	FMOV      Inst = 5045
	FMSUB     Inst = 5149
	FMUL      Inst = 5171
	FMULX     Inst = 5270
	FNEG      Inst = 5369
	FNMADD    Inst = 5408
	FNMSUB    Inst = 5430
	FNMUL     Inst = 5452
	FRECPE    Inst = 5471
	FRECPS    Inst = 5510
	FRECPX    Inst = 5559
	FRINTA    Inst = 5575
	FRINTI    Inst = 5614
	FRINTM    Inst = 5653
	FRINTN    Inst = 5692
	FRINTP    Inst = 5731
	FRINTX    Inst = 5770
	FRINTZ    Inst = 5809
	FRSQRTE   Inst = 5848
	FRSQRTS   Inst = 5887
	FSQRT     Inst = 5936
	FSUB      Inst = 5975
	HINT      Inst = 6024
	HLT       Inst = 6029
	HVC       Inst = 6034
	IC        Inst = 6039
	INS       Inst = 6050
	ISB       Inst = 6103
	LD1       Inst = 6116
	LD1R      Inst = 6773
	LD2       Inst = 6870
	LD2R      Inst = 7099
	LD3       Inst = 7196
	LD3R      Inst = 7425
	LD4       Inst = 7522
	LD4R      Inst = 7751
	LDADD     Inst = 7848
	LDADDA    Inst = 7861
	LDADDAB   Inst = 7874
	LDADDAH   Inst = 7881
	LDADDAL   Inst = 7888
	LDADDALB  Inst = 7901
	LDADDALH  Inst = 7908
	LDADDB    Inst = 7915
	LDADDH    Inst = 7922
	LDADDL    Inst = 7929
	LDADDLB   Inst = 7942
	LDADDLH   Inst = 7949
	LDAPR     Inst = 7956
	LDAPRB    Inst = 7967
	LDAPRH    Inst = 7973
	LDAPUR    Inst = 7979
	LDAPURB   Inst = 7990
	LDAPURH   Inst = 7996
	LDAPURSB  Inst = 8002
	LDAPURSH  Inst = 8013
	LDAPURSW  Inst = 8024
	LDAR      Inst = 8030
	LDARB     Inst = 8041
	LDARH     Inst = 8047
	LDAXP     Inst = 8053
	LDAXR     Inst = 8066
	LDAXRB    Inst = 8077
	LDAXRH    Inst = 8083
	LDCLR     Inst = 8089
	LDCLRA    Inst = 8102
	LDCLRAB   Inst = 8115
	LDCLRAH   Inst = 8122
	LDCLRAL   Inst = 8129
	LDCLRALB  Inst = 8142
	LDCLRALH  Inst = 8149
	LDCLRB    Inst = 8156
	LDCLRH    Inst = 8163
	LDCLRL    Inst = 8170
	LDCLRLB   Inst = 8183
	LDCLRLH   Inst = 8190
	LDEOR     Inst = 8197
	LDEORA    Inst = 8210
	LDEORAB   Inst = 8223
	LDEORAH   Inst = 8230
	LDEORAL   Inst = 8237
	LDEORALB  Inst = 8250
	LDEORALH  Inst = 8257
	LDEORB    Inst = 8264
	LDEORH    Inst = 8271
	LDEORL    Inst = 8278
	LDEORLB   Inst = 8291
	LDEORLH   Inst = 8298
	LDLAR     Inst = 8305
	LDLARB    Inst = 8316
	LDLARH    Inst = 8322
	LDNP      Inst = 8328
	LDP       Inst = 8359
	LDPSW     Inst = 8455
	LDR       Inst = 8475
	LDRAA     Inst = 8648
	LDRAB     Inst = 8659
	LDRB      Inst = 8670
	LDRH      Inst = 8692
	LDRSB     Inst = 8714
	LDRSH     Inst = 8757
	LDRSW     Inst = 8800
	LDSET     Inst = 8827
	LDSETA    Inst = 8840
	LDSETAB   Inst = 8853
	LDSETAH   Inst = 8860
	LDSETAL   Inst = 8867
	LDSETALB  Inst = 8880
	LDSETALH  Inst = 8887
	LDSETB    Inst = 8894
	LDSETH    Inst = 8901
	LDSETL    Inst = 8908
	LDSETLB   Inst = 8921
	LDSETLH   Inst = 8928
	LDSMAX    Inst = 8935
	LDSMAXA   Inst = 8948
	LDSMAXAB  Inst = 8961
	LDSMAXAH  Inst = 8968
	LDSMAXAL  Inst = 8975
	LDSMAXALB Inst = 8988
	LDSMAXALH Inst = 8995
	LDSMAXB   Inst = 9002
	LDSMAXH   Inst = 9009
	LDSMAXL   Inst = 9016
	LDSMAXLB  Inst = 9029
	LDSMAXLH  Inst = 9036
	LDSMIN    Inst = 9043
	LDSMINA   Inst = 9056
	LDSMINAB  Inst = 9069
	LDSMINAH  Inst = 9076
	LDSMINAL  Inst = 9083
	LDSMINALB Inst = 9096
	LDSMINALH Inst = 9103
	LDSMINB   Inst = 9110
	LDSMINH   Inst = 9117
	LDSMINL   Inst = 9124
	LDSMINLB  Inst = 9137
	LDSMINLH  Inst = 9144
	LDTR      Inst = 9151
	LDTRB     Inst = 9162
	LDTRH     Inst = 9168
	LDTRSB    Inst = 9174
	LDTRSH    Inst = 9185
	LDTRSW    Inst = 9196
	LDUMAX    Inst = 9202
	LDUMAXA   Inst = 9215
	LDUMAXAB  Inst = 9228
	LDUMAXAH  Inst = 9235
	LDUMAXAL  Inst = 9242
	LDUMAXALB Inst = 9255
	LDUMAXALH Inst = 9262
	LDUMAXB   Inst = 9269
	LDUMAXH   Inst = 9276
	LDUMAXL   Inst = 9283
	LDUMAXLB  Inst = 9296
	LDUMAXLH  Inst = 9303
	LDUMIN    Inst = 9310
	LDUMINA   Inst = 9323
	LDUMINAB  Inst = 9336
	LDUMINAH  Inst = 9343
	LDUMINAL  Inst = 9350
	LDUMINALB Inst = 9363
	LDUMINALH Inst = 9370
	LDUMINB   Inst = 9377
	LDUMINH   Inst = 9384
	LDUMINL   Inst = 9391
	LDUMINLB  Inst = 9404
	LDUMINLH  Inst = 9411
	LDUR      Inst = 9418
	LDURB     Inst = 9454
	LDURH     Inst = 9460
	LDURSB    Inst = 9466
	LDURSH    Inst = 9477
	LDURSW    Inst = 9488
	LDXP      Inst = 9494
	LDXR      Inst = 9507
	LDXRB     Inst = 9518
	LDXRH     Inst = 9524
	LSL       Inst = 9530
	LSLV      Inst = 9555
	LSR       Inst = 9568
	LSRV      Inst = 9593
	MADD      Inst = 9606
	MLA       Inst = 9621
	MLS       Inst = 9667
	MNEG      Inst = 9713
	MOV       Inst = 9726
	MOVI      Inst = 9880
	MOVK      Inst = 9928
	MOVN      Inst = 9945
	MOVZ      Inst = 9962
	MRS       Inst = 9979
	MSR       Inst = 9985
	MSUB      Inst = 9996
	MUL       Inst = 10011
	MVN       Inst = 10069
	MVNI      Inst = 10093
	NEG       Inst = 10120
	NEGS      Inst = 10172
	NGC       Inst = 10189
	NGCS      Inst = 10200
	NOP       Inst = 10211
	NOT       Inst = 10215
	ORN       Inst = 10223
	ORR       Inst = 10251
	PACDA     Inst = 10309
	PACDB     Inst = 10315
	PACDZA    Inst = 10321
	PACDZB    Inst = 10326
	PACGA     Inst = 10331
	PACIA     Inst = 10338
	PACIA1716 Inst = 10344
	PACIASP   Inst = 10348
	PACIAZ    Inst = 10352
	PACIB     Inst = 10356
	PACIB1716 Inst = 10362
	PACIBSP   Inst = 10366
	PACIBZ    Inst = 10370
	PACIZA    Inst = 10374
	PACIZB    Inst = 10379
	PMUL      Inst = 10384
	PMULL     Inst = 10394
	PMULL2    Inst = 10419
	PRFM      Inst = 10444
	PRFUM     Inst = 10455
	PSB       Inst = 10461
	PSSBB     Inst = 10467
	RADDHN    Inst = 10471
	RADDHN2   Inst = 10508
	RAX1      Inst = 10545
	RBIT      Inst = 10558
	RET       Inst = 10576
	RETAA     Inst = 10584
	RETAB     Inst = 10588
	REV       Inst = 10592
	REV16     Inst = 10603
	REV32     Inst = 10621
	REV64     Inst = 10641
	RMIF      Inst = 10668
	ROR       Inst = 10675
	RORV      Inst = 10700
	RSHRN     Inst = 10713
	RSHRN2    Inst = 10744
	RSUBHN    Inst = 10775
	RSUBHN2   Inst = 10812
	SABA      Inst = 10849
	SABAL     Inst = 10877
	SABAL2    Inst = 10914
	SABD      Inst = 10951
	SABDL     Inst = 10979
	SABDL2    Inst = 11016
	SADALP    Inst = 11053
	SADDL     Inst = 11075
	SADDL2    Inst = 11112
	SADDLP    Inst = 11149
	SADDLV    Inst = 11171
	SADDW     Inst = 11191
	SADDW2    Inst = 11228
	SB        Inst = 11265
	SBC       Inst = 11269
	SBCS      Inst = 11282
	SBFIZ     Inst = 11295
	SBFM      Inst = 11310
	SBFX      Inst = 11325
	SCVTF     Inst = 11340
	SDIV      Inst = 11489
	SDOT      Inst = 11502
	SETF16    Inst = 11551
	SETF8     Inst = 11556
	SEV       Inst = 11561
	SEVL      Inst = 11565
	SHA1C     Inst = 11569
	SHA1H     Inst = 11578
	SHA1M     Inst = 11584
	SHA1P     Inst = 11593
	SHA1SU0   Inst = 11602
	SHA1SU1   Inst = 11615
	SHA256H   Inst = 11625
	SHA256H2  Inst = 11634
	SHA256SU0 Inst = 11643
	SHA256SU1 Inst = 11653
	SHA512H   Inst = 11666
	SHA512H2  Inst = 11675
	SHA512SU0 Inst = 11684
	SHA512SU1 Inst = 11694
	SHADD     Inst = 11707
	SHL       Inst = 11735
	SHLL      Inst = 11776
	SHLL2     Inst = 11810
	SHRN      Inst = 11844
	SHRN2     Inst = 11875
	SHSUB     Inst = 11906
	SLI       Inst = 11934
	SM3PARTW1 Inst = 11975
	SM3PARTW2 Inst = 11988
	SM3SS1    Inst = 12001
	SM3TT1A   Inst = 12017
	SM3TT1B   Inst = 12029
	SM3TT2A   Inst = 12041
	SM3TT2B   Inst = 12053
	SM4E      Inst = 12065
	SM4EKEY   Inst = 12075
	SMADDL    Inst = 12088
	SMAX      Inst = 12096
	SMAXP     Inst = 12124
	SMAXV     Inst = 12152
	SMC       Inst = 12172
	SMIN      Inst = 12177
	SMINP     Inst = 12205
	SMINV     Inst = 12233
	SMLAL     Inst = 12253
	SMLAL2    Inst = 12312
	SMLSL     Inst = 12371
	SMLSL2    Inst = 12430
	SMNEGL    Inst = 12489
	SMOV      Inst = 12496
	SMSUBL    Inst = 12527
	SMULH     Inst = 12535
	SMULL     Inst = 12542
	SMULL2    Inst = 12607
	SQABS     Inst = 12666
	SQADD     Inst = 12717
	SQDMLAL   Inst = 12781
	SQDMLAL2  Inst = 12854
	SQDMLSL   Inst = 12901
	SQDMLSL2  Inst = 12974
	SQDMULH   Inst = 13021
	SQDMULL   Inst = 13084
	SQDMULL2  Inst = 13157
	SQNEG     Inst = 13204
	SQRDMLAH  Inst = 13255
	SQRDMLSH  Inst = 13318
	SQRDMULH  Inst = 13381
	SQRSHL    Inst = 13444
	SQRSHRN   Inst = 13508
	SQRSHRN2  Inst = 13557
	SQRSHRUN  Inst = 13588
	SQRSHRUN2 Inst = 13637
	SQSHL     Inst = 13668
	SQSHLU    Inst = 13790
	SQSHRN    Inst = 13849
	SQSHRN2   Inst = 13898
	SQSHRUN   Inst = 13929
	SQSHRUN2  Inst = 13978
	SQSUB     Inst = 14009
	SQXTN     Inst = 14073
	SQXTN2    Inst = 14116
	SQXTUN    Inst = 14144
	SQXTUN2   Inst = 14187
	SRHADD    Inst = 14215
	SRI       Inst = 14243
	SRSHL     Inst = 14284
	SRSHR     Inst = 14330
	SRSRA     Inst = 14371
	SSBB      Inst = 14412
	SSHL      Inst = 14416
	SSHLL     Inst = 14462
	SSHLL2    Inst = 14493
	SSHR      Inst = 14524
	SSRA      Inst = 14565
	SSUBL     Inst = 14606
	SSUBL2    Inst = 14643
	SSUBW     Inst = 14680
	SSUBW2    Inst = 14717
	ST1       Inst = 14754
	ST2       Inst = 15411
	ST3       Inst = 15640
	ST4       Inst = 15869
	STADD     Inst = 16098
	STADDB    Inst = 16109
	STADDH    Inst = 16115
	STADDL    Inst = 16121
	STADDLB   Inst = 16132
	STADDLH   Inst = 16138
	STCLR     Inst = 16144
	STCLRB    Inst = 16155
	STCLRH    Inst = 16161
	STCLRL    Inst = 16167
	STCLRLB   Inst = 16178
	STCLRLH   Inst = 16184
	STEOR     Inst = 16190
	STEORB    Inst = 16201
	STEORH    Inst = 16207
	STEORL    Inst = 16213
	STEORLB   Inst = 16224
	STEORLH   Inst = 16230
	STLLR     Inst = 16236
	STLLRB    Inst = 16247
	STLLRH    Inst = 16253
	STLR      Inst = 16259
	STLRB     Inst = 16270
	STLRH     Inst = 16276
	STLUR     Inst = 16282
	STLURB    Inst = 16293
	STLURH    Inst = 16299
	STLXP     Inst = 16305
	STLXR     Inst = 16320
	STLXRB    Inst = 16333
	STLXRH    Inst = 16340
	STNP      Inst = 16347
	STP       Inst = 16378
	STR       Inst = 16474
	STRB      Inst = 16622
	STRH      Inst = 16644
	STSET     Inst = 16666
	STSETB    Inst = 16677
	STSETH    Inst = 16683
	STSETL    Inst = 16689
	STSETLB   Inst = 16700
	STSETLH   Inst = 16706
	STSMAX    Inst = 16712
	STSMAXB   Inst = 16723
	STSMAXH   Inst = 16729
	STSMAXL   Inst = 16735
	STSMAXLB  Inst = 16746
	STSMAXLH  Inst = 16752
	STSMIN    Inst = 16758
	STSMINB   Inst = 16769
	STSMINH   Inst = 16775
	STSMINL   Inst = 16781
	STSMINLB  Inst = 16792
	STSMINLH  Inst = 16798
	STTR      Inst = 16804
	STTRB     Inst = 16815
	STTRH     Inst = 16821
	STUMAX    Inst = 16827
	STUMAXB   Inst = 16838
	STUMAXH   Inst = 16844
	STUMAXL   Inst = 16850
	STUMAXLB  Inst = 16861
	STUMAXLH  Inst = 16867
	STUMIN    Inst = 16873
	STUMINB   Inst = 16884
	STUMINH   Inst = 16890
	STUMINL   Inst = 16896
	STUMINLB  Inst = 16907
	STUMINLH  Inst = 16913
	STUR      Inst = 16919
	STURB     Inst = 16955
	STURH     Inst = 16961
	STXP      Inst = 16967
	STXR      Inst = 16982
	STXRB     Inst = 16995
	STXRH     Inst = 17002
	SUB       Inst = 17009
	SUBHN     Inst = 17118
	SUBHN2    Inst = 17155
	SUBS      Inst = 17192
	SUQADD    Inst = 17256
	SVC       Inst = 17307
	SWP       Inst = 17312
	SWPA      Inst = 17325
	SWPAB     Inst = 17338
	SWPAH     Inst = 17345
	SWPAL     Inst = 17352
	SWPALB    Inst = 17365
	SWPALH    Inst = 17372
	SWPB      Inst = 17379
	SWPH      Inst = 17386
	SWPL      Inst = 17393
	SWPLB     Inst = 17406
	SWPLH     Inst = 17413
	SXTB      Inst = 17420
	SXTH      Inst = 17431
	SXTL      Inst = 17442
	SXTL2     Inst = 17470
	SXTW      Inst = 17498
	SYS       Inst = 17504
	SYSL      Inst = 17514
	TBL       Inst = 17523
	TBNZ      Inst = 17568
	TBX       Inst = 17581
	TBZ       Inst = 17626
	TLBI      Inst = 17639
	TRN1      Inst = 17646
	TRN2      Inst = 17686
	TSB       Inst = 17726
	TST       Inst = 17732
	UABA      Inst = 17759
	UABAL     Inst = 17787
	UABAL2    Inst = 17824
	UABD      Inst = 17861
	UABDL     Inst = 17889
	UABDL2    Inst = 17926
	UADALP    Inst = 17963
	UADDL     Inst = 17985
	UADDL2    Inst = 18022
	UADDLP    Inst = 18059
	UADDLV    Inst = 18081
	UADDW     Inst = 18101
	UADDW2    Inst = 18138
	UBFIZ     Inst = 18175
	UBFM      Inst = 18190
	UBFX      Inst = 18205
	UCVTF     Inst = 18220
	UDF       Inst = 18369
	UDIV      Inst = 18374
	UDOT      Inst = 18387
	UHADD     Inst = 18436
	UHSUB     Inst = 18464
	UMADDL    Inst = 18492
	UMAX      Inst = 18500
	UMAXP     Inst = 18528
	UMAXV     Inst = 18556
	UMIN      Inst = 18576
	UMINP     Inst = 18604
	UMINV     Inst = 18632
	UMLAL     Inst = 18652
	UMLAL2    Inst = 18711
	UMLSL     Inst = 18770
	UMLSL2    Inst = 18829
	UMNEGL    Inst = 18888
	UMOV      Inst = 18895
	UMSUBL    Inst = 18920
	UMULH     Inst = 18928
	UMULL     Inst = 18935
	UMULL2    Inst = 19000
	UQADD     Inst = 19059
	UQRSHL    Inst = 19123
	UQRSHRN   Inst = 19187
	UQRSHRN2  Inst = 19236
	UQSHL     Inst = 19267
	UQSHRN    Inst = 19389
	UQSHRN2   Inst = 19438
	UQSUB     Inst = 19469
	UQXTN     Inst = 19533
	UQXTN2    Inst = 19576
	URECPE    Inst = 19604
	URHADD    Inst = 19612
	URSHL     Inst = 19640
	URSHR     Inst = 19686
	URSQRTE   Inst = 19727
	URSRA     Inst = 19735
	USHL      Inst = 19776
	USHLL     Inst = 19822
	USHLL2    Inst = 19853
	USHR      Inst = 19884
	USQADD    Inst = 19925
	USRA      Inst = 19976
	USUBL     Inst = 20017
	USUBL2    Inst = 20054
	USUBW     Inst = 20091
	USUBW2    Inst = 20128
	UXTB      Inst = 20165
	UXTH      Inst = 20171
	UXTL      Inst = 20177
	UXTL2     Inst = 20205
	UZP1      Inst = 20233
	UZP2      Inst = 20273
	WFE       Inst = 20313
	WFI       Inst = 20317
	XAR       Inst = 20321
	XPACD     Inst = 20335
	XPACI     Inst = 20340
	XPACLRI   Inst = 20345
	XTN       Inst = 20349
	XTN2      Inst = 20377
	YIELD     Inst = 20405
	ZIP1      Inst = 20409
	ZIP2      Inst = 20449
)

Instructions

type Label 

type Label struct {
	ID     uint32 // generated label identifier
	Offset int32  // optional offset from label
}

Label is a label reference argument with an optional offset from the label.

type Mod 

type Mod struct {
	ID     uint8 // modifier symbol
	ImmInv uint8 // bitwise complement, zero indicates unset
}

Mod is a shift, rotate, or extension modifier argument. Shift and rotate modifiers require an immediate.

The following modifiers are available:

func (Mod) GetImm 

func (m Mod) GetImm() uint8

GetImm returns the immediate shift or rotate amount for m. The amount is only valid if HasImm returns true.

func (Mod) HasImm 

func (m Mod) HasImm() bool

HasImm returns true if an immediate shift or rotate amount is set for m.

func (Mod) Imm 

func (m Mod) Imm(i uint8) Mod

Imm constructs a modifier argument from m with an immediate shift or rotate amount.

type Ref 

type Ref struct {
	Base Reg // X|SP
}

Ref is a memory reference argument with a register base. For post-indexing, a Ref may be followed by an X register or immediate offset.

type RefIndexed 

type RefIndexed struct {
	Base Reg // X|SP
	Idx  Reg // X|W
	Mod  Mod // Idx=X: LSL|SXTX, Idx=W: SXTW|UXTW; LSL requires imm
}

RefIndexed is an memory reference argument with a register base, register index, and optional index modifier.

type RefOffset 

type RefOffset struct {
	Base   Reg // X|SP
	Offset int32
}

RefOffset is a memory reference argument with a register base and immediate offset.

type RefPreIndexed 

type RefPreIndexed struct {
	Base   Reg // X|SP
	Offset int32
}

RefPreIndexed is a pre-indexed memory reference argument with a register base and immediate offset.

type Reg 

type Reg struct {
	ID      uint8   // 0-31 register number
	Type    RegType // element size; integer, SP, or SIMD register type; 34/64/128-bit indicator
	ElemInv uint8   // vector element index (bitwise complement, zero indicates unset)
}

Reg is a scalar or vector register argument. Vector registers may include an element specifier.

The following register constructors and values are available:

func ScalarB 

func ScalarB(id uint8) Reg

ScalarB constructs an 8-bit scalar SIMD register, with type RB and family RegFloat.

func ScalarD 

func ScalarD(id uint8) Reg

ScalarD constructs a 64-bit scalar SIMD register, with type RD and family RegFloat.

func ScalarH 

func ScalarH(id uint8) Reg

ScalarH constructs a 16-bit scalar SIMD register, with type RH and family RegFloat.

func ScalarQ 

func ScalarQ(id uint8) Reg

ScalarQ constructs a 16-bit scalar SIMD register, with type RQ and family RegFloat.

func ScalarS 

func ScalarS(id uint8) Reg

ScalarS constructs a 32-bit scalar SIMD register, with type RS and family RegFloat.

func Vec16B 

func Vec16B(id uint8) Reg

Vec16B constructs a 16x8-bit vector SIMD register, with type V16B and family RegVec128.

func Vec1D 

func Vec1D(id uint8) Reg

Vec1D constructs a 1x64-bit vector SIMD register, with type V1D and family RegVec64.

func Vec1Q 

func Vec1Q(id uint8) Reg

Vec1Q constructs a 1x128-bit vector SIMD register, with type V1Q and family RegVec128.

func Vec2D 

func Vec2D(id uint8) Reg

Vec2D constructs a 2x64-bit vector SIMD register, with type V2D and family RegVec128.

func Vec2H 

func Vec2H(id uint8) Reg

Vec2H constructs a 2x16-bit vector SIMD register, with type V2H and family RegVec32.

func Vec2S 

func Vec2S(id uint8) Reg

Vec2S constructs a 2x32-bit vector SIMD register, with type V2S and family RegVec64.

func Vec4B 

func Vec4B(id uint8) Reg

Vec4B constructs a 4x8-bit vector SIMD register, with type V4B and family RegVec32.

func Vec4H 

func Vec4H(id uint8) Reg

Vec4H constructs a 4x16-bit vector SIMD register, with type V4H and family RegVec64.

func Vec4S 

func Vec4S(id uint8) Reg

Vec4S constructs a 4x32-bit vector SIMD register, with type V4S and family RegVec128.

func Vec8B 

func Vec8B(id uint8) Reg

Vec8B constructs an 8x8-bit vector SIMD register, with type V8B and family RegVec64.

func Vec8H 

func Vec8H(id uint8) Reg

Vec8H constructs a 8x16-bit vector SIMD register, with type V8H and family RegVec128.

func W 

func W(id uint8) Reg

W constructs a 32-bit integer register, with type RW and family RegInt.

func X 

func X(id uint8) Reg

X constructs a 64-bit integer register, with type RX and family RegInt.

func (Reg) ElemSize 

func (r Reg) ElemSize() Size

ElemSize returns the element size for r. For vector registers, the size represents a single lane.

func (Reg) Family 

func (r Reg) Family() RegFamily

Family returns the register family for r (integer, SP, scalar, vector).

func (Reg) GetElem 

func (r Reg) GetElem() uint8

GetElem returns the vector element selected for r. The element is only valid if HasElem returns true.

func (Reg) HasElem 

func (r Reg) HasElem() bool

HasElem returns true if a vector element is selected for r.

func (Reg) I 

func (r Reg) I(idx uint8) Reg

I selects a vector element from r.

func (Reg) IsVec 

func (r Reg) IsVec() bool

IsVec returns true is the type of r is a vector type.

func (Reg) Lanes 

func (r Reg) Lanes() uint8

Lanes returns the number of lanes for the type of r.

func (Reg) List 

func (r Reg) List(length uint8) RegList

List constructs a register list with sequential registers starting from r.

type RegFamily 

type RegFamily uint8

RegFamily represents the family of a register (integer, SP, scalar, vector). 

const (
	RegInt    RegFamily // X and W registers (except stack pointer)
	RegSP               // stack pointer registers
	RegFloat            // scalar simd registers
	RegVec32            // 32-bit vector registers
	RegVec64            // 64-bit vector registers
	RegVec128           // 128-bit vector registers
)

type RegList 

type RegList struct {
	First Reg
	Len   uint8
}

RegList is a register list argument with sequentially numbered registers (modulo 32).

func (RegList) I 

func (r RegList) I(idx uint8) RegList

I selects a vector element from all registers in r.

type RegType 

type RegType uint8

RegType indicates an element size, family, and lane count for a register. 

const (
	RW RegType = RegType(DWORD) | RegType(RegInt<<4) // RW represents 32-bit integer registers
	RX RegType = RegType(QWORD) | RegType(RegInt<<4) // RX represents 64-bit integer registers

	RWSP RegType = RegType(DWORD) | RegType(RegSP<<4) // RWSP represents 32-bit stack pointer registers
	RXSP RegType = RegType(QWORD) | RegType(RegSP<<4) // RXSP represents 64-bit stack pointer registers

	RB RegType = RegType(BYTE) | RegType(RegFloat<<4)  // RB represents 8-bit scalar SIMD registers
	RH RegType = RegType(WORD) | RegType(RegFloat<<4)  // RH represents 16-bit scalar SIMD registers
	RS RegType = RegType(DWORD) | RegType(RegFloat<<4) // RS represents 32-bit scalar SIMD registers
	RD RegType = RegType(QWORD) | RegType(RegFloat<<4) // RD represents 64-bit scalar SIMD registers
	RQ RegType = RegType(OWORD) | RegType(RegFloat<<4) // RQ represents 128-bit scalar SIMD registers

	V4B  RegType = RegType(BYTE) | RegType(RegVec32<<4)   // V4B represents 4x8-bit vector SIMD registers
	V8B  RegType = RegType(BYTE) | RegType(RegVec64<<4)   // V8B represents 8x8-bit vector SIMD registers
	V16B RegType = RegType(BYTE) | RegType(RegVec128<<4)  // V16B represents 16x8-bit vector SIMD registers
	V2H  RegType = RegType(WORD) | RegType(RegVec32<<4)   // V2H represents 2x16-bit vector SIMD registers
	V4H  RegType = RegType(WORD) | RegType(RegVec64<<4)   // V4H represents 4x16-bit vector SIMD registers
	V8H  RegType = RegType(WORD) | RegType(RegVec128<<4)  // V8H represents 8x16-bit vector SIMD registers
	V2S  RegType = RegType(DWORD) | RegType(RegVec64<<4)  // V2S represents 2x32-bit vector SIMD registers
	V4S  RegType = RegType(DWORD) | RegType(RegVec128<<4) // V4S represents 4x32-bit vector SIMD registers
	V1D  RegType = RegType(QWORD) | RegType(RegVec64<<4)  // V1D represents 1x64-bit vector SIMD registers
	V2D  RegType = RegType(QWORD) | RegType(RegVec128<<4) // V2D represents 2x64-bit vector SIMD registers
	V1Q  RegType = RegType(OWORD) | RegType(RegVec128<<4) // V1Q represents 1x128-bit vector SIMD registers
)

func (RegType) Bytes 

func (sz RegType) Bytes() uint8

ElemBytes returns the full size in bytes for sz. For vector registers, the size represents all lanes combined.

func (RegType) Elem 

func (sz RegType) Elem() Size

Elem returns the element size for sz. For vector registers, the size represents a single lane.

func (RegType) ElemBytes 

func (sz RegType) ElemBytes() uint8

ElemBytes returns the element size in bytes for sz. For vector registers, the size represents a single lane.

func (RegType) Family 

func (sz RegType) Family() RegFamily

Family returns the register family for sz (integer, SP, scalar, vector).

func (RegType) Lanes 

func (sz RegType) Lanes() uint8

Lanes returns the lane count for sz. If sz is not from a vector register family, the lane count is 0.

type Reloc 

type Reloc struct {
	InstPC uint32    // instruction with label offset argument
	Op     uint8     // relocation type
	Jump   FlatLabel // label ID with optional offset
}

Reloc is a Label reference deferred for encoding after all relocations are being applied. Relocations are used internally, and exposed for debugging.

type Size 

type Size uint8

Size represents the width of a register elememt. 

const (
	BYTE  Size // 8-bit register elements
	WORD       // 16-bit register elements
	DWORD      // 32-bit register elements
	QWORD      // 64-bit register elements
	OWORD      // 128-bit register element
)

type Symbol 

type Symbol uint8

Symbol is a symbol/identifier argument. 

const (
	EQ Symbol = 0 + 1
	NE Symbol = 1 + 1
	CS Symbol = 2 + 1
	HS Symbol = 2 + 1
	CC Symbol = 3 + 1
	LO Symbol = 3 + 1
	MI Symbol = 4 + 1
	PL Symbol = 5 + 1
	VS Symbol = 6 + 1
	VC Symbol = 7 + 1
	HI Symbol = 8 + 1
	LS Symbol = 9 + 1
	GE Symbol = 10 + 1
	LT Symbol = 11 + 1
	GT Symbol = 12 + 1
	LE Symbol = 13 + 1
	AL Symbol = 14 + 1
	NV Symbol = 15 + 1
)

Condition code symbols 

const (
	RCTX     Symbol // restriction by context
	IVAU            // instruction cache line invalidation
	INVERTED        // inverted moves
	LOGICAL         // logical moves
	CSYNC           // profile/trace synchronization

	C0  // CONTROLREGS (Control Registers)
	C1  // CONTROLREGS (Control Registers)
	C2  // CONTROLREGS (Control Registers)
	C3  // CONTROLREGS (Control Registers)
	C4  // CONTROLREGS (Control Registers)
	C5  // CONTROLREGS (Control Registers)
	C6  // CONTROLREGS (Control Registers)
	C7  // CONTROLREGS (Control Registers)
	C8  // CONTROLREGS (Control Registers)
	C9  // CONTROLREGS (Control Registers)
	C10 // CONTROLREGS (Control Registers)
	C11 // CONTROLREGS (Control Registers)
	C12 // CONTROLREGS (Control Registers)
	C13 // CONTROLREGS (Control Registers)
	C14 // CONTROLREGS (Control Registers)
	C15 // CONTROLREGS (Control Registers)

	S1E1R  // ATOPS (Address Translation)
	S1E1W  // ATOPS (Address Translation)
	S1E0R  // ATOPS (Address Translation)
	S1E0W  // ATOPS (Address Translation)
	S1E2R  // ATOPS (Address Translation)
	S1E2W  // ATOPS (Address Translation)
	S12E1R // ATOPS (Address Translation)
	S12E1W // ATOPS (Address Translation)
	S12E0R // ATOPS (Address Translation)
	S12E0W // ATOPS (Address Translation)
	S1E3R  // ATOPS (Address Translation)
	S1E3W  // ATOPS (Address Translation)
	S1E1RP // ATOPS (Address Translation)
	S1E1WP // ATOPS (Address Translation)

	IALLUIS // ICOPS (Instruction Cache)
	IALLU   // ICOPS (Instruction Cache)

	IVAC  // DCOPS (Data Cache)
	ISW   // DCOPS (Data Cache)
	CSW   // DCOPS (Data Cache)
	CISW  // DCOPS (Data Cache)
	ZVA   // DCOPS (Data Cache)
	CVAC  // DCOPS (Data Cache)
	CVAU  // DCOPS (Data Cache)
	CIVAC // DCOPS (Data Cache)
	CVAP  // DCOPS (Data Cache)

	SY    // BARRIEROPS (Instruction/Data Synchronization Barriers)
	ST    // BARRIEROPS (Instruction/Data Synchronization Barriers)
	LD    // BARRIEROPS (Instruction/Data Synchronization Barriers)
	ISH   // BARRIEROPS (Instruction/Data Synchronization Barriers)
	ISHST // BARRIEROPS (Instruction/Data Synchronization Barriers)
	ISHLD // BARRIEROPS (Instruction/Data Synchronization Barriers)
	NSH   // BARRIEROPS (Instruction/Data Synchronization Barriers)
	NSHST // BARRIEROPS (Instruction/Data Synchronization Barriers)
	NSHLD // BARRIEROPS (Instruction/Data Synchronization Barriers)
	OSH   // BARRIEROPS (Instruction/Data Synchronization Barriers)
	OSHST // BARRIEROPS (Instruction/Data Synchronization Barriers)
	OSHLD // BARRIEROPS (Instruction/Data Synchronization Barriers)

	SPSEL        // MSRIMMOPS (System Registers)
	DAIFSET      // MSRIMMOPS (System Registers)
	DAIFCLR      // MSRIMMOPS (System Registers)
	UAO          // MSRIMMOPS (System Registers)
	PAN          // MSRIMMOPS (System Registers)
	DIT          // MSRIMMOPS (System Registers)
	VMALLE1IS    // MSRIMMOPS (System Registers)
	VAE1IS       // MSRIMMOPS (System Registers)
	ASIDE1IS     // MSRIMMOPS (System Registers)
	VAAE1IS      // MSRIMMOPS (System Registers)
	VALE1IS      // MSRIMMOPS (System Registers)
	VAALE1IS     // MSRIMMOPS (System Registers)
	VMALLE1      // MSRIMMOPS (System Registers)
	VAE1         // MSRIMMOPS (System Registers)
	ASIDE1       // MSRIMMOPS (System Registers)
	VAAE1        // MSRIMMOPS (System Registers)
	VALE1        // MSRIMMOPS (System Registers)
	VAALE1       // MSRIMMOPS (System Registers)
	IPAS2E1IS    // MSRIMMOPS (System Registers)
	IPAS2LE1IS   // MSRIMMOPS (System Registers)
	ALLE2IS      // MSRIMMOPS (System Registers)
	VAE2IS       // MSRIMMOPS (System Registers)
	ALLE1IS      // MSRIMMOPS (System Registers)
	VALE2IS      // MSRIMMOPS (System Registers)
	VMALLS12E1IS // MSRIMMOPS (System Registers)
	IPAS2E1      // MSRIMMOPS (System Registers)
	IPAS2LE1     // MSRIMMOPS (System Registers)
	ALLE2        // MSRIMMOPS (System Registers)
	VAE2         // MSRIMMOPS (System Registers)
	ALLE1        // MSRIMMOPS (System Registers)
	VALE2        // MSRIMMOPS (System Registers)
	VMALLS12E1   // MSRIMMOPS (System Registers)
	ALLE3IS      // MSRIMMOPS (System Registers)
	VAE3IS       // MSRIMMOPS (System Registers)
	VALE3IS      // MSRIMMOPS (System Registers)
	ALLE3        // MSRIMMOPS (System Registers)
	VAE3         // MSRIMMOPS (System Registers)
	VALE3        // MSRIMMOPS (System Registers)
	VMALLE1OS    // MSRIMMOPS (System Registers)
	VAE1OS       // MSRIMMOPS (System Registers)
	ASIDE1OS     // MSRIMMOPS (System Registers)
	VAAE1OS      // MSRIMMOPS (System Registers)
	VALE1OS      // MSRIMMOPS (System Registers)
	VAALE1OS     // MSRIMMOPS (System Registers)
	RVAE1IS      // MSRIMMOPS (System Registers)
	RVAAE1IS     // MSRIMMOPS (System Registers)
	RVALE1IS     // MSRIMMOPS (System Registers)
	RVAALE1IS    // MSRIMMOPS (System Registers)
	RVAE1OS      // MSRIMMOPS (System Registers)
	RVAAE1OS     // MSRIMMOPS (System Registers)
	RVALE1OS     // MSRIMMOPS (System Registers)
	RVAALE1OS    // MSRIMMOPS (System Registers)
	RVAE1        // MSRIMMOPS (System Registers)
	RVAAE1       // MSRIMMOPS (System Registers)
	RVALE1       // MSRIMMOPS (System Registers)
	RVAALE1      // MSRIMMOPS (System Registers)
	RIPAS2E1IS   // MSRIMMOPS (System Registers)
	RIPAS2LE1IS  // MSRIMMOPS (System Registers)
	ALLE2OS      // MSRIMMOPS (System Registers)
	VAE2OS       // MSRIMMOPS (System Registers)
	ALLE1OS      // MSRIMMOPS (System Registers)
	VALE2OS      // MSRIMMOPS (System Registers)

	VMALLS12E1OS // TLBIOPS (Translation Table)
	RVAE2IS      // TLBIOPS (Translation Table)
	RVALE2IS     // TLBIOPS (Translation Table)
	IPAS2E1OS    // TLBIOPS (Translation Table)
	RIPAS2E1     // TLBIOPS (Translation Table)
	RIPAS2E1OS   // TLBIOPS (Translation Table)
	IPAS2LE1OS   // TLBIOPS (Translation Table)
	RIPAS2LE1    // TLBIOPS (Translation Table)
	RIPAS2LE1OS  // TLBIOPS (Translation Table)
	RVAE2OS      // TLBIOPS (Translation Table)
	RVALE2OS     // TLBIOPS (Translation Table)
	RVAE2        // TLBIOPS (Translation Table)
	RVALE2       // TLBIOPS (Translation Table)
	ALLE3OS      // TLBIOPS (Translation Table)
	VAE3OS       // TLBIOPS (Translation Table)
	VALE3OS      // TLBIOPS (Translation Table)
	RVAE3IS      // TLBIOPS (Translation Table)
	RVALE3IS     // TLBIOPS (Translation Table)
	RVAE3OS      // TLBIOPS (Translation Table)
	RVALE3OS     // TLBIOPS (Translation Table)
	RVAE3        // TLBIOPS (Translation Table)
	RVALE3       // TLBIOPS (Translation Table)
)

type Wide 

type Wide uint64

Wide is a 64-bit integer immediate argument.

Source Files

View all Source files

Directories

Path Synopsis
gen
inst
inst/instref
inst/opmap

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