Documentation

Overview

    Package cpu implements processor feature detection used by the Go standard library.

    Index

    Constants

    View Source
    const CacheLinePadSize = 64
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    const GOARCH = "amd64"

    Variables

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    var ARM struct {
    	HasVFPv4 bool
    	HasIDIVA bool
    	// contains filtered or unexported fields
    }

      The booleans in ARM contain the correspondingly named cpu feature bit. The struct is padded to avoid false sharing.

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      var ARM64 struct {
      	HasAES       bool
      	HasPMULL     bool
      	HasSHA1      bool
      	HasSHA2      bool
      	HasCRC32     bool
      	HasATOMICS   bool
      	HasCPUID     bool
      	IsNeoverseN1 bool
      	IsZeus       bool
      	// contains filtered or unexported fields
      }

        The booleans in ARM64 contain the correspondingly named cpu feature bit. The struct is padded to avoid false sharing.

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        var CacheLineSize uintptr = CacheLinePadSize

          CacheLineSize is the CPU's assumed cache line size. There is currently no runtime detection of the real cache line size so we use the constant per GOARCH CacheLinePadSize as an approximation.

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          var DebugOptions bool

            DebugOptions is set to true by the runtime if the OS supports reading GODEBUG early in runtime startup. This should not be changed after it is initialized.

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            var MIPS64X struct {
            	HasMSA bool // MIPS SIMD architecture
            	// contains filtered or unexported fields
            }
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            var PPC64 struct {
            	HasDARN  bool // Hardware random number generator (requires kernel enablement)
            	HasSCV   bool // Syscall vectored (requires kernel enablement)
            	IsPOWER8 bool // ISA v2.07 (POWER8)
            	IsPOWER9 bool // ISA v3.00 (POWER9)
            	// contains filtered or unexported fields
            }

              For ppc64(le), it is safe to check only for ISA level starting on ISA v3.00, since there are no optional categories. There are some exceptions that also require kernel support to work (darn, scv), so there are feature bits for those as well. The minimum processor requirement is POWER8 (ISA 2.07). The struct is padded to avoid false sharing.

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              var S390X struct {
              	HasZARCH  bool // z architecture mode is active [mandatory]
              	HasSTFLE  bool // store facility list extended [mandatory]
              	HasLDISP  bool // long (20-bit) displacements [mandatory]
              	HasEIMM   bool // 32-bit immediates [mandatory]
              	HasDFP    bool // decimal floating point
              	HasETF3EH bool // ETF-3 enhanced
              	HasMSA    bool // message security assist (CPACF)
              	HasAES    bool // KM-AES{128,192,256} functions
              	HasAESCBC bool // KMC-AES{128,192,256} functions
              	HasAESCTR bool // KMCTR-AES{128,192,256} functions
              	HasAESGCM bool // KMA-GCM-AES{128,192,256} functions
              	HasGHASH  bool // KIMD-GHASH function
              	HasSHA1   bool // K{I,L}MD-SHA-1 functions
              	HasSHA256 bool // K{I,L}MD-SHA-256 functions
              	HasSHA512 bool // K{I,L}MD-SHA-512 functions
              	HasSHA3   bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions
              	HasVX     bool // vector facility. Note: the runtime sets this when it processes auxv records.
              	HasVXE    bool // vector-enhancements facility 1
              	HasKDSA   bool // elliptic curve functions
              	HasECDSA  bool // NIST curves
              	HasEDDSA  bool // Edwards curves
              	// contains filtered or unexported fields
              }
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              var X86 struct {
              	HasAES       bool
              	HasADX       bool
              	HasAVX       bool
              	HasAVX2      bool
              	HasBMI1      bool
              	HasBMI2      bool
              	HasERMS      bool
              	HasFMA       bool
              	HasOSXSAVE   bool
              	HasPCLMULQDQ bool
              	HasPOPCNT    bool
              	HasSSE2      bool
              	HasSSE3      bool
              	HasSSSE3     bool
              	HasSSE41     bool
              	HasSSE42     bool
              	// contains filtered or unexported fields
              }

                The booleans in X86 contain the correspondingly named cpuid feature bit. HasAVX and HasAVX2 are only set if the OS does support XMM and YMM registers in addition to the cpuid feature bit being set. The struct is padded to avoid false sharing.

                Functions

                func Initialize added in go1.12

                func Initialize(env string)

                  Initialize examines the processor and sets the relevant variables above. This is called by the runtime package early in program initialization, before normal init functions are run. env is set by runtime if the OS supports cpu feature options in GODEBUG.

                  func Name added in go1.16

                  func Name() string

                    Name returns the CPU name given by the vendor. If the CPU name can not be determined an empty string is returned.

                    Types

                    type CacheLinePad added in go1.12

                    type CacheLinePad struct {
                    	// contains filtered or unexported fields
                    }

                      CacheLinePad is used to pad structs to avoid false sharing.