Versions in this module Expand all Collapse all v0 v0.0.2 Aug 4, 2024 Changes in this version + var AdrAESAccelerator = AddressCellObj + var AdrCacheMMUTable = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_EFUSE_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_EMAC_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_GPIO_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_HINF_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_I2S0_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_I2S1_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_LEDC_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_PCNT_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_PWM0_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_PWM1_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_PWR_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_RMT_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_RTC_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SLC_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SPI0_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SPI1_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SPI2_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SPI3_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_UART1_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_UART2_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_UART_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_UHCI0_REG = AddressCellObj + var AdrDPORT_AHBLITE_MPU_TABLE_UHCI1_REG = AddressCellObj + var AdrDPORT_AHB_MPU_TABLE_0_REG = AddressCellObj + var AdrDPORT_AHB_MPU_TABLE_1_REG = AddressCellObj + var AdrDPORT_APPCPU_CTRL_REG_A_REG = AddressCellObj + var AdrDPORT_APPCPU_CTRL_REG_B_REG = AddressCellObj + var AdrDPORT_APPCPU_CTRL_REG_C_REG = AddressCellObj + var AdrDPORT_APPCPU_CTRL_REG_D_REG = AddressCellObj + var AdrDPORT_APP_BB_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_BOOT_REMAP_CTRL_REG = AddressCellObj + var AdrDPORT_APP_BT_BB_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_BT_BB_NMI_MAP_REG = AddressCellObj + var AdrDPORT_APP_BT_MAC_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_CACHE_CTRL1_REG = AddressCellObj + var AdrDPORT_APP_CACHE_CTRL_REG = AddressCellObj + var AdrDPORT_APP_CACHE_IA_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG = AddressCellObj + var AdrDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG = AddressCellObj + var AdrDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG = AddressCellObj + var AdrDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG = AddressCellObj + var AdrDPORT_APP_EFUSE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_EMAC_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_GPIO_INTERRUPT_MAP_REG = AddressCellObj + var AdrDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG = AddressCellObj + var AdrDPORT_APP_I2C_EXT0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_I2C_EXT1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_I2S0_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_I2S1_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_INTR_STATUS_REG_0_REG = AddressCellObj + var AdrDPORT_APP_INTR_STATUS_REG_1_REG = AddressCellObj + var AdrDPORT_APP_INTR_STATUS_REG_2_REG = AddressCellObj + var AdrDPORT_APP_LEDC_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_MAC_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_MAC_NMI_MAP_REG = AddressCellObj + var AdrDPORT_APP_MMU_IA_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_MPU_IA_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_PCNT_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_PWM0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_PWM1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_RMT_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_RSA_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_RTC_CORE_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_RWBLE_IRQ_MAP_REG = AddressCellObj + var AdrDPORT_APP_RWBLE_NMI_MAP_REG = AddressCellObj + var AdrDPORT_APP_RWBT_IRQ_MAP_REG = AddressCellObj + var AdrDPORT_APP_RWBT_NMI_MAP_REG = AddressCellObj + var AdrDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG = AddressCellObj + var AdrDPORT_APP_SLC0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_SLC1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_SPI1_DMA_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_SPI2_DMA_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_SPI3_DMA_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_SPI_INTR_0_MAP_REG = AddressCellObj + var AdrDPORT_APP_SPI_INTR_1_MAP_REG = AddressCellObj + var AdrDPORT_APP_SPI_INTR_2_MAP_REG = AddressCellObj + var AdrDPORT_APP_SPI_INTR_3_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_T0_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_T1_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_LACT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_T0_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_T0_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_T1_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_T1_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_WDT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_TIMER_INT1_MAP_REG = AddressCellObj + var AdrDPORT_APP_TIMER_INT2_MAP_REG = AddressCellObj + var AdrDPORT_APP_TWAI_INT_MAP_REG = AddressCellObj + var AdrDPORT_APP_UART1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_UART2_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_UART_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_UHCI0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_UHCI1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_APP_WDG_INT_MAP_REG = AddressCellObj + var AdrDPORT_CACHE_MUX_MODE_REG = AddressCellObj + var AdrDPORT_CPU_INTR_FROM_CPU_0_REG = AddressCellObj + var AdrDPORT_CPU_INTR_FROM_CPU_1_REG = AddressCellObj + var AdrDPORT_CPU_INTR_FROM_CPU_2_REG = AddressCellObj + var AdrDPORT_CPU_INTR_FROM_CPU_3_REG = AddressCellObj + var AdrDPORT_CPU_PER_CONF_REG = AddressCellObj + var AdrDPORT_DMMU_PAGE_MODE_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE0_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE10_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE11_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE12_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE13_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE14_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE15_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE1_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE2_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE3_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE4_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE5_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE6_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE7_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE8_REG = AddressCellObj + var AdrDPORT_DMMU_TABLE9_REG = AddressCellObj + var AdrDPORT_IMMU_PAGE_MODE_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE0_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE10_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE11_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE12_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE13_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE14_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE15_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE1_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE2_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE3_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE4_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE5_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE6_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE7_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE8_REG = AddressCellObj + var AdrDPORT_IMMU_TABLE9_REG = AddressCellObj + var AdrDPORT_PERIP_CLK_EN_REG = AddressCellObj + var AdrDPORT_PERIP_RST_EN_REG = AddressCellObj + var AdrDPORT_PERI_CLK_EN_REG = AddressCellObj + var AdrDPORT_PERI_RST_EN_REG = AddressCellObj + var AdrDPORT_PRO_BB_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_BOOT_REMAP_CTRL_REG = AddressCellObj + var AdrDPORT_PRO_BT_BB_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_BT_BB_NMI_MAP_REG = AddressCellObj + var AdrDPORT_PRO_BT_MAC_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_CACHE_CTRL1_REG = AddressCellObj + var AdrDPORT_PRO_CACHE_CTRL_REG = AddressCellObj + var AdrDPORT_PRO_CACHE_IA_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG = AddressCellObj + var AdrDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG = AddressCellObj + var AdrDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG = AddressCellObj + var AdrDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG = AddressCellObj + var AdrDPORT_PRO_EFUSE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_EMAC_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_GPIO_INTERRUPT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG = AddressCellObj + var AdrDPORT_PRO_I2C_EXT0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_I2C_EXT1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_I2S0_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_I2S1_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_INTR_STATUS_REG_0_REG = AddressCellObj + var AdrDPORT_PRO_INTR_STATUS_REG_1_REG = AddressCellObj + var AdrDPORT_PRO_INTR_STATUS_REG_2_REG = AddressCellObj + var AdrDPORT_PRO_LEDC_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_MAC_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_MAC_NMI_MAP_REG = AddressCellObj + var AdrDPORT_PRO_MMU_IA_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_MPU_IA_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_PCNT_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_PWM0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_PWM1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_RMT_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_RSA_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_RTC_CORE_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_RWBLE_IRQ_MAP_REG = AddressCellObj + var AdrDPORT_PRO_RWBLE_NMI_MAP_REG = AddressCellObj + var AdrDPORT_PRO_RWBT_IRQ_MAP_REG = AddressCellObj + var AdrDPORT_PRO_RWBT_NMI_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SLC0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SLC1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SPI1_DMA_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SPI2_DMA_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SPI3_DMA_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SPI_INTR_0_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SPI_INTR_1_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SPI_INTR_2_MAP_REG = AddressCellObj + var AdrDPORT_PRO_SPI_INTR_3_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_T0_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_T1_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TIMER_INT1_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TIMER_INT2_MAP_REG = AddressCellObj + var AdrDPORT_PRO_TWAI_INT_MAP_REG = AddressCellObj + var AdrDPORT_PRO_UART1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_UART2_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_UART_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_UHCI0_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_UHCI1_INTR_MAP_REG = AddressCellObj + var AdrDPORT_PRO_WDG_INT_MAP_REG = AddressCellObj + var AdrDPORT_SPI_DMA_CHAN_SEL_REG = AddressCellObj + var AdrDPORT_WIFI_CLK_EN_REG = AddressCellObj + var AdrDPORT_WIFI_RST_EN_REG = AddressCellObj + var AdrDPortRegister = AddressCellObj + var AdrEFuseController = AddressCellObj + var AdrEMAC = AddressCellObj + var AdrFlashEncryption = AddressCellObj + var AdrGPIO = AddressCellObj + var AdrI2C0 = AddressCellObj + var AdrI2C1 = AddressCellObj + var AdrI2S0 = AddressCellObj + var AdrI2S1 = AddressCellObj + var AdrIOMUX = AddressCellObj + var AdrLEDPWM = AddressCellObj + var AdrMCPWM0 = AddressCellObj + var AdrMCPWM1 = AddressCellObj + var AdrPCNT = AddressCellObj + var AdrPIDController = AddressCellObj + var AdrRMT = AddressCellObj + var AdrRNG = AddressCellObj + var AdrRSAAccelerator = AddressCellObj + var AdrRTC = AddressCellObj + var AdrSDIOSlave1 = AddressCellObj + var AdrSDIOSlave2 = AddressCellObj + var AdrSDIOSlave3 = AddressCellObj + var AdrSDMMC = AddressCellObj + var AdrSHAAccelerator = AddressCellObj + var AdrSPI0 = AddressCellObj + var AdrSPI1 = AddressCellObj + var AdrSPI2 = AddressCellObj + var AdrSPI3 = AddressCellObj + var AdrSYSCON = AddressCellObj + var AdrSYSCON_APLL_TICK_CONF_REG = AddressCellObj + var AdrSYSCON_CK8M_TICK_CONF_REG = AddressCellObj + var AdrSYSCON_DATE_REG = AddressCellObj + var AdrSYSCON_PLL_TICK_CONF_REG = AddressCellObj + var AdrSYSCON_SYSCLK_CONF_REG = AddressCellObj + var AdrSYSCON_XTAL_TICK_CONF_REG = AddressCellObj + var AdrSecureBoot = AddressCellObj + var AdrTIMG0 = AddressCellObj + var AdrTIMG1 = AddressCellObj + var AdrTWAI = AddressCellObj + var AdrUART0 = AddressCellObj + var AdrUART1 = AddressCellObj + var AdrUART2 = AddressCellObj + var AdrUDMA0 = AddressCellObj + var AdrUDMA1 = AddressCellObj + var DPortMap = map[DPortType]*AddressCellObj + var PeripheralMap = map[PeripheralType]*AddressCellObj + var SysConMap = map[SysConType]*AddressCellObj + type AddressCellObj struct + Begin AddressType + End AddressType + func (adr *AddressCellObj) Size() AddressType + type AddressType uint64 + const AdrBeginAESAccelerator + const AdrBeginCacheMMUTable + const AdrBeginDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_EFUSE_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_EMAC_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_GPIO_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_HINF_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_I2S0_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_I2S1_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_LEDC_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_PCNT_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_PWM0_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_PWM1_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_PWR_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_RMT_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_RTC_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SLC_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI0_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI1_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI2_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI3_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_UART1_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_UART2_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_UART_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_UHCI0_REG + const AdrBeginDPORT_AHBLITE_MPU_TABLE_UHCI1_REG + const AdrBeginDPORT_AHB_MPU_TABLE_0_REG + const AdrBeginDPORT_AHB_MPU_TABLE_1_REG + const AdrBeginDPORT_APPCPU_CTRL_REG_A_REG + const AdrBeginDPORT_APPCPU_CTRL_REG_B_REG + const AdrBeginDPORT_APPCPU_CTRL_REG_C_REG + const AdrBeginDPORT_APPCPU_CTRL_REG_D_REG + const AdrBeginDPORT_APP_BB_INT_MAP_REG + const AdrBeginDPORT_APP_BOOT_REMAP_CTRL_REG + const AdrBeginDPORT_APP_BT_BB_INT_MAP_REG + const AdrBeginDPORT_APP_BT_BB_NMI_MAP_REG + const AdrBeginDPORT_APP_BT_MAC_INT_MAP_REG + const AdrBeginDPORT_APP_CACHE_CTRL1_REG + const AdrBeginDPORT_APP_CACHE_CTRL_REG + const AdrBeginDPORT_APP_CACHE_IA_INT_MAP_REG + const AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG + const AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG + const AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG + const AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG + const AdrBeginDPORT_APP_EFUSE_INT_MAP_REG + const AdrBeginDPORT_APP_EMAC_INT_MAP_REG + const AdrBeginDPORT_APP_GPIO_INTERRUPT_MAP_REG + const AdrBeginDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG + const AdrBeginDPORT_APP_I2C_EXT0_INTR_MAP_REG + const AdrBeginDPORT_APP_I2C_EXT1_INTR_MAP_REG + const AdrBeginDPORT_APP_I2S0_INT_MAP_REG + const AdrBeginDPORT_APP_I2S1_INT_MAP_REG + const AdrBeginDPORT_APP_INTR_STATUS_REG_0_REG + const AdrBeginDPORT_APP_INTR_STATUS_REG_1_REG + const AdrBeginDPORT_APP_INTR_STATUS_REG_2_REG + const AdrBeginDPORT_APP_LEDC_INT_MAP_REG + const AdrBeginDPORT_APP_MAC_INTR_MAP_REG + const AdrBeginDPORT_APP_MAC_NMI_MAP_REG + const AdrBeginDPORT_APP_MMU_IA_INT_MAP_REG + const AdrBeginDPORT_APP_MPU_IA_INT_MAP_REG + const AdrBeginDPORT_APP_PCNT_INTR_MAP_REG + const AdrBeginDPORT_APP_PWM0_INTR_MAP_REG + const AdrBeginDPORT_APP_PWM1_INTR_MAP_REG + const AdrBeginDPORT_APP_RMT_INTR_MAP_REG + const AdrBeginDPORT_APP_RSA_INTR_MAP_REG + const AdrBeginDPORT_APP_RTC_CORE_INTR_MAP_REG + const AdrBeginDPORT_APP_RWBLE_IRQ_MAP_REG + const AdrBeginDPORT_APP_RWBLE_NMI_MAP_REG + const AdrBeginDPORT_APP_RWBT_IRQ_MAP_REG + const AdrBeginDPORT_APP_RWBT_NMI_MAP_REG + const AdrBeginDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG + const AdrBeginDPORT_APP_SLC0_INTR_MAP_REG + const AdrBeginDPORT_APP_SLC1_INTR_MAP_REG + const AdrBeginDPORT_APP_SPI1_DMA_INT_MAP_REG + const AdrBeginDPORT_APP_SPI2_DMA_INT_MAP_REG + const AdrBeginDPORT_APP_SPI3_DMA_INT_MAP_REG + const AdrBeginDPORT_APP_SPI_INTR_0_MAP_REG + const AdrBeginDPORT_APP_SPI_INTR_1_MAP_REG + const AdrBeginDPORT_APP_SPI_INTR_2_MAP_REG + const AdrBeginDPORT_APP_SPI_INTR_3_MAP_REG + const AdrBeginDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TG1_T0_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TG1_T1_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TG_LACT_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TG_T0_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG_T0_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TG_T1_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG_T1_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TG_WDT_EDGE_INT_MAP_REG + const AdrBeginDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_APP_TIMER_INT1_MAP_REG + const AdrBeginDPORT_APP_TIMER_INT2_MAP_REG + const AdrBeginDPORT_APP_TWAI_INT_MAP_REG + const AdrBeginDPORT_APP_UART1_INTR_MAP_REG + const AdrBeginDPORT_APP_UART2_INTR_MAP_REG + const AdrBeginDPORT_APP_UART_INTR_MAP_REG + const AdrBeginDPORT_APP_UHCI0_INTR_MAP_REG + const AdrBeginDPORT_APP_UHCI1_INTR_MAP_REG + const AdrBeginDPORT_APP_WDG_INT_MAP_REG + const AdrBeginDPORT_CACHE_MUX_MODE_REG + const AdrBeginDPORT_CPU_INTR_FROM_CPU_0_REG + const AdrBeginDPORT_CPU_INTR_FROM_CPU_1_REG + const AdrBeginDPORT_CPU_INTR_FROM_CPU_2_REG + const AdrBeginDPORT_CPU_INTR_FROM_CPU_3_REG + const AdrBeginDPORT_CPU_PER_CONF_REG + const AdrBeginDPORT_DMMU_PAGE_MODE_REG + const AdrBeginDPORT_DMMU_TABLE0_REG + const AdrBeginDPORT_DMMU_TABLE10_REG + const AdrBeginDPORT_DMMU_TABLE11_REG + const AdrBeginDPORT_DMMU_TABLE12_REG + const AdrBeginDPORT_DMMU_TABLE13_REG + const AdrBeginDPORT_DMMU_TABLE14_REG + const AdrBeginDPORT_DMMU_TABLE15_REG + const AdrBeginDPORT_DMMU_TABLE1_REG + const AdrBeginDPORT_DMMU_TABLE2_REG + const AdrBeginDPORT_DMMU_TABLE3_REG + const AdrBeginDPORT_DMMU_TABLE4_REG + const AdrBeginDPORT_DMMU_TABLE5_REG + const AdrBeginDPORT_DMMU_TABLE6_REG + const AdrBeginDPORT_DMMU_TABLE7_REG + const AdrBeginDPORT_DMMU_TABLE8_REG + const AdrBeginDPORT_DMMU_TABLE9_REG + const AdrBeginDPORT_IMMU_PAGE_MODE_REG + const AdrBeginDPORT_IMMU_TABLE0_REG + const AdrBeginDPORT_IMMU_TABLE10_REG + const AdrBeginDPORT_IMMU_TABLE11_REG + const AdrBeginDPORT_IMMU_TABLE12_REG + const AdrBeginDPORT_IMMU_TABLE13_REG + const AdrBeginDPORT_IMMU_TABLE14_REG + const AdrBeginDPORT_IMMU_TABLE15_REG + const AdrBeginDPORT_IMMU_TABLE1_REG + const AdrBeginDPORT_IMMU_TABLE2_REG + const AdrBeginDPORT_IMMU_TABLE3_REG + const AdrBeginDPORT_IMMU_TABLE4_REG + const AdrBeginDPORT_IMMU_TABLE5_REG + const AdrBeginDPORT_IMMU_TABLE6_REG + const AdrBeginDPORT_IMMU_TABLE7_REG + const AdrBeginDPORT_IMMU_TABLE8_REG + const AdrBeginDPORT_IMMU_TABLE9_REG + const AdrBeginDPORT_PERIP_CLK_EN_REG + const AdrBeginDPORT_PERIP_RST_EN_REG + const AdrBeginDPORT_PERI_CLK_EN_REG + const AdrBeginDPORT_PERI_RST_EN_REG + const AdrBeginDPORT_PRO_BB_INT_MAP_REG + const AdrBeginDPORT_PRO_BOOT_REMAP_CTRL_REG + const AdrBeginDPORT_PRO_BT_BB_INT_MAP_REG + const AdrBeginDPORT_PRO_BT_BB_NMI_MAP_REG + const AdrBeginDPORT_PRO_BT_MAC_INT_MAP_REG + const AdrBeginDPORT_PRO_CACHE_CTRL1_REG + const AdrBeginDPORT_PRO_CACHE_CTRL_REG + const AdrBeginDPORT_PRO_CACHE_IA_INT_MAP_REG + const AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG + const AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG + const AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG + const AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG + const AdrBeginDPORT_PRO_EFUSE_INT_MAP_REG + const AdrBeginDPORT_PRO_EMAC_INT_MAP_REG + const AdrBeginDPORT_PRO_GPIO_INTERRUPT_MAP_REG + const AdrBeginDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG + const AdrBeginDPORT_PRO_I2C_EXT0_INTR_MAP_REG + const AdrBeginDPORT_PRO_I2C_EXT1_INTR_MAP_REG + const AdrBeginDPORT_PRO_I2S0_INT_MAP_REG + const AdrBeginDPORT_PRO_I2S1_INT_MAP_REG + const AdrBeginDPORT_PRO_INTR_STATUS_REG_0_REG + const AdrBeginDPORT_PRO_INTR_STATUS_REG_1_REG + const AdrBeginDPORT_PRO_INTR_STATUS_REG_2_REG + const AdrBeginDPORT_PRO_LEDC_INT_MAP_REG + const AdrBeginDPORT_PRO_MAC_INTR_MAP_REG + const AdrBeginDPORT_PRO_MAC_NMI_MAP_REG + const AdrBeginDPORT_PRO_MMU_IA_INT_MAP_REG + const AdrBeginDPORT_PRO_MPU_IA_INT_MAP_REG + const AdrBeginDPORT_PRO_PCNT_INTR_MAP_REG + const AdrBeginDPORT_PRO_PWM0_INTR_MAP_REG + const AdrBeginDPORT_PRO_PWM1_INTR_MAP_REG + const AdrBeginDPORT_PRO_RMT_INTR_MAP_REG + const AdrBeginDPORT_PRO_RSA_INTR_MAP_REG + const AdrBeginDPORT_PRO_RTC_CORE_INTR_MAP_REG + const AdrBeginDPORT_PRO_RWBLE_IRQ_MAP_REG + const AdrBeginDPORT_PRO_RWBLE_NMI_MAP_REG + const AdrBeginDPORT_PRO_RWBT_IRQ_MAP_REG + const AdrBeginDPORT_PRO_RWBT_NMI_MAP_REG + const AdrBeginDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG + const AdrBeginDPORT_PRO_SLC0_INTR_MAP_REG + const AdrBeginDPORT_PRO_SLC1_INTR_MAP_REG + const AdrBeginDPORT_PRO_SPI1_DMA_INT_MAP_REG + const AdrBeginDPORT_PRO_SPI2_DMA_INT_MAP_REG + const AdrBeginDPORT_PRO_SPI3_DMA_INT_MAP_REG + const AdrBeginDPORT_PRO_SPI_INTR_0_MAP_REG + const AdrBeginDPORT_PRO_SPI_INTR_1_MAP_REG + const AdrBeginDPORT_PRO_SPI_INTR_2_MAP_REG + const AdrBeginDPORT_PRO_SPI_INTR_3_MAP_REG + const AdrBeginDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_T0_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_T1_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG + const AdrBeginDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG + const AdrBeginDPORT_PRO_TIMER_INT1_MAP_REG + const AdrBeginDPORT_PRO_TIMER_INT2_MAP_REG + const AdrBeginDPORT_PRO_TWAI_INT_MAP_REG + const AdrBeginDPORT_PRO_UART1_INTR_MAP_REG + const AdrBeginDPORT_PRO_UART2_INTR_MAP_REG + const AdrBeginDPORT_PRO_UART_INTR_MAP_REG + const AdrBeginDPORT_PRO_UHCI0_INTR_MAP_REG + const AdrBeginDPORT_PRO_UHCI1_INTR_MAP_REG + const AdrBeginDPORT_PRO_WDG_INT_MAP_REG + const AdrBeginDPORT_SPI_DMA_CHAN_SEL_REG + const AdrBeginDPORT_WIFI_CLK_EN_REG + const AdrBeginDPORT_WIFI_RST_EN_REG + const AdrBeginDPortRegister + const AdrBeginEFuseController + const AdrBeginEMAC + const AdrBeginFlashEncryption + const AdrBeginGPIO + const AdrBeginI2C0 + const AdrBeginI2C1 + const AdrBeginI2S0 + const AdrBeginI2S1 + const AdrBeginIOMUX + const AdrBeginLEDPWM + const AdrBeginMCPWM0 + const AdrBeginMCPWM1 + const AdrBeginPCNT + const AdrBeginPIDController + const AdrBeginRMT + const AdrBeginRNG + const AdrBeginRSAAccelerator + const AdrBeginRTC + const AdrBeginSDIOSlave1 + const AdrBeginSDIOSlave2 + const AdrBeginSDIOSlave3 + const AdrBeginSDMMC + const AdrBeginSHAAccelerator + const AdrBeginSPI0 + const AdrBeginSPI1 + const AdrBeginSPI2 + const AdrBeginSPI3 + const AdrBeginSYSCON + const AdrBeginSYSCON_APLL_TICK_CONF_REG + const AdrBeginSYSCON_CK8M_TICK_CONF_REG + const AdrBeginSYSCON_DATE_REG + const AdrBeginSYSCON_PLL_TICK_CONF_REG + const AdrBeginSYSCON_SYSCLK_CONF_REG + const AdrBeginSYSCON_XTAL_TICK_CONF_REG + const AdrBeginSecureBoot + const AdrBeginTIMG0 + const AdrBeginTIMG1 + const AdrBeginTWAI + const AdrBeginUART0 + const AdrBeginUART1 + const AdrBeginUART2 + const AdrBeginUDMA0 + const AdrBeginUDMA1 + const AdrEndAESAccelerator + const AdrEndCacheMMUTable + const AdrEndDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_EFUSE_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_EMAC_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_GPIO_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_HINF_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_I2S0_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_I2S1_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_LEDC_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_PCNT_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_PWM0_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_PWM1_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_PWR_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_RMT_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_RTC_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SLC_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SPI0_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SPI1_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SPI2_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SPI3_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_UART1_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_UART2_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_UART_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_UHCI0_REG + const AdrEndDPORT_AHBLITE_MPU_TABLE_UHCI1_REG + const AdrEndDPORT_AHB_MPU_TABLE_0_REG + const AdrEndDPORT_AHB_MPU_TABLE_1_REG + const AdrEndDPORT_APPCPU_CTRL_REG_A_REG + const AdrEndDPORT_APPCPU_CTRL_REG_B_REG + const AdrEndDPORT_APPCPU_CTRL_REG_C_REG + const AdrEndDPORT_APPCPU_CTRL_REG_D_REG + const AdrEndDPORT_APP_BB_INT_MAP_REG + const AdrEndDPORT_APP_BOOT_REMAP_CTRL_REG + const AdrEndDPORT_APP_BT_BB_INT_MAP_REG + const AdrEndDPORT_APP_BT_BB_NMI_MAP_REG + const AdrEndDPORT_APP_BT_MAC_INT_MAP_REG + const AdrEndDPORT_APP_CACHE_CTRL1_REG + const AdrEndDPORT_APP_CACHE_CTRL_REG + const AdrEndDPORT_APP_CACHE_IA_INT_MAP_REG + const AdrEndDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG + const AdrEndDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG + const AdrEndDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG + const AdrEndDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG + const AdrEndDPORT_APP_EFUSE_INT_MAP_REG + const AdrEndDPORT_APP_EMAC_INT_MAP_REG + const AdrEndDPORT_APP_GPIO_INTERRUPT_MAP_REG + const AdrEndDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG + const AdrEndDPORT_APP_I2C_EXT0_INTR_MAP_REG + const AdrEndDPORT_APP_I2C_EXT1_INTR_MAP_REG + const AdrEndDPORT_APP_I2S0_INT_MAP_REG + const AdrEndDPORT_APP_I2S1_INT_MAP_REG + const AdrEndDPORT_APP_INTR_STATUS_REG_0_REG + const AdrEndDPORT_APP_INTR_STATUS_REG_1_REG + const AdrEndDPORT_APP_INTR_STATUS_REG_2_REG + const AdrEndDPORT_APP_LEDC_INT_MAP_REG + const AdrEndDPORT_APP_MAC_INTR_MAP_REG + const AdrEndDPORT_APP_MAC_NMI_MAP_REG + const AdrEndDPORT_APP_MMU_IA_INT_MAP_REG + const AdrEndDPORT_APP_MPU_IA_INT_MAP_REG + const AdrEndDPORT_APP_PCNT_INTR_MAP_REG + const AdrEndDPORT_APP_PWM0_INTR_MAP_REG + const AdrEndDPORT_APP_PWM1_INTR_MAP_REG + const AdrEndDPORT_APP_RMT_INTR_MAP_REG + const AdrEndDPORT_APP_RSA_INTR_MAP_REG + const AdrEndDPORT_APP_RTC_CORE_INTR_MAP_REG + const AdrEndDPORT_APP_RWBLE_IRQ_MAP_REG + const AdrEndDPORT_APP_RWBLE_NMI_MAP_REG + const AdrEndDPORT_APP_RWBT_IRQ_MAP_REG + const AdrEndDPORT_APP_RWBT_NMI_MAP_REG + const AdrEndDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG + const AdrEndDPORT_APP_SLC0_INTR_MAP_REG + const AdrEndDPORT_APP_SLC1_INTR_MAP_REG + const AdrEndDPORT_APP_SPI1_DMA_INT_MAP_REG + const AdrEndDPORT_APP_SPI2_DMA_INT_MAP_REG + const AdrEndDPORT_APP_SPI3_DMA_INT_MAP_REG + const AdrEndDPORT_APP_SPI_INTR_0_MAP_REG + const AdrEndDPORT_APP_SPI_INTR_1_MAP_REG + const AdrEndDPORT_APP_SPI_INTR_2_MAP_REG + const AdrEndDPORT_APP_SPI_INTR_3_MAP_REG + const AdrEndDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TG1_T0_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TG1_T1_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TG_LACT_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TG_T0_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG_T0_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TG_T1_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG_T1_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TG_WDT_EDGE_INT_MAP_REG + const AdrEndDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG + const AdrEndDPORT_APP_TIMER_INT1_MAP_REG + const AdrEndDPORT_APP_TIMER_INT2_MAP_REG + const AdrEndDPORT_APP_TWAI_INT_MAP_REG + const AdrEndDPORT_APP_UART1_INTR_MAP_REG + const AdrEndDPORT_APP_UART2_INTR_MAP_REG + const AdrEndDPORT_APP_UART_INTR_MAP_REG + const AdrEndDPORT_APP_UHCI0_INTR_MAP_REG + const AdrEndDPORT_APP_UHCI1_INTR_MAP_REG + const AdrEndDPORT_APP_WDG_INT_MAP_REG + const AdrEndDPORT_CACHE_MUX_MODE_REG + const AdrEndDPORT_CPU_INTR_FROM_CPU_0_REG + const AdrEndDPORT_CPU_INTR_FROM_CPU_1_REG + const AdrEndDPORT_CPU_INTR_FROM_CPU_2_REG + const AdrEndDPORT_CPU_INTR_FROM_CPU_3_REG + const AdrEndDPORT_CPU_PER_CONF_REG + const AdrEndDPORT_DMMU_PAGE_MODE_REG + const AdrEndDPORT_DMMU_TABLE0_REG + const AdrEndDPORT_DMMU_TABLE10_REG + const AdrEndDPORT_DMMU_TABLE11_REG + const AdrEndDPORT_DMMU_TABLE12_REG + const AdrEndDPORT_DMMU_TABLE13_REG + const AdrEndDPORT_DMMU_TABLE14_REG + const AdrEndDPORT_DMMU_TABLE15_REG + const AdrEndDPORT_DMMU_TABLE1_REG + const AdrEndDPORT_DMMU_TABLE2_REG + const AdrEndDPORT_DMMU_TABLE3_REG + const AdrEndDPORT_DMMU_TABLE4_REG + const AdrEndDPORT_DMMU_TABLE5_REG + const AdrEndDPORT_DMMU_TABLE6_REG + const AdrEndDPORT_DMMU_TABLE7_REG + const AdrEndDPORT_DMMU_TABLE8_REG + const AdrEndDPORT_DMMU_TABLE9_REG + const AdrEndDPORT_IMMU_PAGE_MODE_REG + const AdrEndDPORT_IMMU_TABLE0_REG + const AdrEndDPORT_IMMU_TABLE10_REG + const AdrEndDPORT_IMMU_TABLE11_REG + const AdrEndDPORT_IMMU_TABLE12_REG + const AdrEndDPORT_IMMU_TABLE13_REG + const AdrEndDPORT_IMMU_TABLE14_REG + const AdrEndDPORT_IMMU_TABLE15_REG + const AdrEndDPORT_IMMU_TABLE1_REG + const AdrEndDPORT_IMMU_TABLE2_REG + const AdrEndDPORT_IMMU_TABLE3_REG + const AdrEndDPORT_IMMU_TABLE4_REG + const AdrEndDPORT_IMMU_TABLE5_REG + const AdrEndDPORT_IMMU_TABLE6_REG + const AdrEndDPORT_IMMU_TABLE7_REG + const AdrEndDPORT_IMMU_TABLE8_REG + const AdrEndDPORT_IMMU_TABLE9_REG + const AdrEndDPORT_PERIP_CLK_EN_REG + const AdrEndDPORT_PERIP_RST_EN_REG + const AdrEndDPORT_PERI_CLK_EN_REG + const AdrEndDPORT_PERI_RST_EN_REG + const AdrEndDPORT_PRO_BB_INT_MAP_REG + const AdrEndDPORT_PRO_BOOT_REMAP_CTRL_REG + const AdrEndDPORT_PRO_BT_BB_INT_MAP_REG + const AdrEndDPORT_PRO_BT_BB_NMI_MAP_REG + const AdrEndDPORT_PRO_BT_MAC_INT_MAP_REG + const AdrEndDPORT_PRO_CACHE_CTRL1_REG + const AdrEndDPORT_PRO_CACHE_CTRL_REG + const AdrEndDPORT_PRO_CACHE_IA_INT_MAP_REG + const AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG + const AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG + const AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG + const AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG + const AdrEndDPORT_PRO_EFUSE_INT_MAP_REG + const AdrEndDPORT_PRO_EMAC_INT_MAP_REG + const AdrEndDPORT_PRO_GPIO_INTERRUPT_MAP_REG + const AdrEndDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG + const AdrEndDPORT_PRO_I2C_EXT0_INTR_MAP_REG + const AdrEndDPORT_PRO_I2C_EXT1_INTR_MAP_REG + const AdrEndDPORT_PRO_I2S0_INT_MAP_REG + const AdrEndDPORT_PRO_I2S1_INT_MAP_REG + const AdrEndDPORT_PRO_INTR_STATUS_REG_0_REG + const AdrEndDPORT_PRO_INTR_STATUS_REG_1_REG + const AdrEndDPORT_PRO_INTR_STATUS_REG_2_REG + const AdrEndDPORT_PRO_LEDC_INT_MAP_REG + const AdrEndDPORT_PRO_MAC_INTR_MAP_REG + const AdrEndDPORT_PRO_MAC_NMI_MAP_REG + const AdrEndDPORT_PRO_MMU_IA_INT_MAP_REG + const AdrEndDPORT_PRO_MPU_IA_INT_MAP_REG + const AdrEndDPORT_PRO_PCNT_INTR_MAP_REG + const AdrEndDPORT_PRO_PWM0_INTR_MAP_REG + const AdrEndDPORT_PRO_PWM1_INTR_MAP_REG + const AdrEndDPORT_PRO_RMT_INTR_MAP_REG + const AdrEndDPORT_PRO_RSA_INTR_MAP_REG + const AdrEndDPORT_PRO_RTC_CORE_INTR_MAP_REG + const AdrEndDPORT_PRO_RWBLE_IRQ_MAP_REG + const AdrEndDPORT_PRO_RWBLE_NMI_MAP_REG + const AdrEndDPORT_PRO_RWBT_IRQ_MAP_REG + const AdrEndDPORT_PRO_RWBT_NMI_MAP_REG + const AdrEndDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG + const AdrEndDPORT_PRO_SLC0_INTR_MAP_REG + const AdrEndDPORT_PRO_SLC1_INTR_MAP_REG + const AdrEndDPORT_PRO_SPI1_DMA_INT_MAP_REG + const AdrEndDPORT_PRO_SPI2_DMA_INT_MAP_REG + const AdrEndDPORT_PRO_SPI3_DMA_INT_MAP_REG + const AdrEndDPORT_PRO_SPI_INTR_0_MAP_REG + const AdrEndDPORT_PRO_SPI_INTR_1_MAP_REG + const AdrEndDPORT_PRO_SPI_INTR_2_MAP_REG + const AdrEndDPORT_PRO_SPI_INTR_3_MAP_REG + const AdrEndDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TG_T0_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TG_T1_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG + const AdrEndDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG + const AdrEndDPORT_PRO_TIMER_INT1_MAP_REG + const AdrEndDPORT_PRO_TIMER_INT2_MAP_REG + const AdrEndDPORT_PRO_TWAI_INT_MAP_REG + const AdrEndDPORT_PRO_UART1_INTR_MAP_REG + const AdrEndDPORT_PRO_UART2_INTR_MAP_REG + const AdrEndDPORT_PRO_UART_INTR_MAP_REG + const AdrEndDPORT_PRO_UHCI0_INTR_MAP_REG + const AdrEndDPORT_PRO_UHCI1_INTR_MAP_REG + const AdrEndDPORT_PRO_WDG_INT_MAP_REG + const AdrEndDPORT_SPI_DMA_CHAN_SEL_REG + const AdrEndDPORT_WIFI_CLK_EN_REG + const AdrEndDPORT_WIFI_RST_EN_REG + const AdrEndDPortRegister + const AdrEndEFuseController + const AdrEndEMAC + const AdrEndFlashEncryption + const AdrEndGPIO + const AdrEndI2C0 + const AdrEndI2C1 + const AdrEndI2S0 + const AdrEndI2S1 + const AdrEndIOMUX + const AdrEndLEDPWM + const AdrEndMCPWM0 + const AdrEndMCPWM1 + const AdrEndPCNT + const AdrEndPIDController + const AdrEndRMT + const AdrEndRNG + const AdrEndRSAAccelerator + const AdrEndRTC + const AdrEndSDIOSlave1 + const AdrEndSDIOSlave2 + const AdrEndSDIOSlave3 + const AdrEndSDMMC + const AdrEndSHAAccelerator + const AdrEndSPI0 + const AdrEndSPI1 + const AdrEndSPI2 + const AdrEndSPI3 + const AdrEndSYSCON + const AdrEndSYSCON_APLL_TICK_CONF_REG + const AdrEndSYSCON_CK8M_TICK_CONF_REG + const AdrEndSYSCON_DATE_REG + const AdrEndSYSCON_PLL_TICK_CONF_REG + const AdrEndSYSCON_SYSCLK_CONF_REG + const AdrEndSYSCON_XTAL_TICK_CONF_REG + const AdrEndSecureBoot + const AdrEndTIMG0 + const AdrEndTIMG1 + const AdrEndTWAI + const AdrEndUART0 + const AdrEndUART1 + const AdrEndUART2 + const AdrEndUDMA0 + const AdrEndUDMA1 + type DPortType byte + const DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG + const DPORT_AHBLITE_MPU_TABLE_EFUSE_REG + const DPORT_AHBLITE_MPU_TABLE_EMAC_REG + const DPORT_AHBLITE_MPU_TABLE_GPIO_REG + const DPORT_AHBLITE_MPU_TABLE_HINF_REG + const DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG + const DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG + const DPORT_AHBLITE_MPU_TABLE_I2S0_REG + const DPORT_AHBLITE_MPU_TABLE_I2S1_REG + const DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG + const DPORT_AHBLITE_MPU_TABLE_LEDC_REG + const DPORT_AHBLITE_MPU_TABLE_PCNT_REG + const DPORT_AHBLITE_MPU_TABLE_PWM0_REG + const DPORT_AHBLITE_MPU_TABLE_PWM1_REG + const DPORT_AHBLITE_MPU_TABLE_PWR_REG + const DPORT_AHBLITE_MPU_TABLE_RMT_REG + const DPORT_AHBLITE_MPU_TABLE_RTC_REG + const DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG + const DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG + const DPORT_AHBLITE_MPU_TABLE_SLC_REG + const DPORT_AHBLITE_MPU_TABLE_SPI0_REG + const DPORT_AHBLITE_MPU_TABLE_SPI1_REG + const DPORT_AHBLITE_MPU_TABLE_SPI2_REG + const DPORT_AHBLITE_MPU_TABLE_SPI3_REG + const DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG + const DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG + const DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG + const DPORT_AHBLITE_MPU_TABLE_UART1_REG + const DPORT_AHBLITE_MPU_TABLE_UART2_REG + const DPORT_AHBLITE_MPU_TABLE_UART_REG + const DPORT_AHBLITE_MPU_TABLE_UHCI0_REG + const DPORT_AHBLITE_MPU_TABLE_UHCI1_REG + const DPORT_AHB_MPU_TABLE_0_REG + const DPORT_AHB_MPU_TABLE_1_REG + const DPORT_APPCPU_CTRL_REG_A_REG + const DPORT_APPCPU_CTRL_REG_B_REG + const DPORT_APPCPU_CTRL_REG_C_REG + const DPORT_APPCPU_CTRL_REG_D_REG + const DPORT_APP_BB_INT_MAP_REG + const DPORT_APP_BOOT_REMAP_CTRL_REG + const DPORT_APP_BT_BB_INT_MAP_REG + const DPORT_APP_BT_BB_NMI_MAP_REG + const DPORT_APP_BT_MAC_INT_MAP_REG + const DPORT_APP_CACHE_CTRL1_REG + const DPORT_APP_CACHE_CTRL_REG + const DPORT_APP_CACHE_IA_INT_MAP_REG + const DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG + const DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG + const DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG + const DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG + const DPORT_APP_EFUSE_INT_MAP_REG + const DPORT_APP_EMAC_INT_MAP_REG + const DPORT_APP_GPIO_INTERRUPT_MAP_REG + const DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG + const DPORT_APP_I2C_EXT0_INTR_MAP_REG + const DPORT_APP_I2C_EXT1_INTR_MAP_REG + const DPORT_APP_I2S0_INT_MAP_REG + const DPORT_APP_I2S1_INT_MAP_REG + const DPORT_APP_INTR_STATUS_REG_0_REG + const DPORT_APP_INTR_STATUS_REG_1_REG + const DPORT_APP_INTR_STATUS_REG_2_REG + const DPORT_APP_LEDC_INT_MAP_REG + const DPORT_APP_MAC_INTR_MAP_REG + const DPORT_APP_MAC_NMI_MAP_REG + const DPORT_APP_MMU_IA_INT_MAP_REG + const DPORT_APP_MPU_IA_INT_MAP_REG + const DPORT_APP_PCNT_INTR_MAP_REG + const DPORT_APP_PWM0_INTR_MAP_REG + const DPORT_APP_PWM1_INTR_MAP_REG + const DPORT_APP_RMT_INTR_MAP_REG + const DPORT_APP_RSA_INTR_MAP_REG + const DPORT_APP_RTC_CORE_INTR_MAP_REG + const DPORT_APP_RWBLE_IRQ_MAP_REG + const DPORT_APP_RWBLE_NMI_MAP_REG + const DPORT_APP_RWBT_IRQ_MAP_REG + const DPORT_APP_RWBT_NMI_MAP_REG + const DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG + const DPORT_APP_SLC0_INTR_MAP_REG + const DPORT_APP_SLC1_INTR_MAP_REG + const DPORT_APP_SPI1_DMA_INT_MAP_REG + const DPORT_APP_SPI2_DMA_INT_MAP_REG + const DPORT_APP_SPI3_DMA_INT_MAP_REG + const DPORT_APP_SPI_INTR_0_MAP_REG + const DPORT_APP_SPI_INTR_1_MAP_REG + const DPORT_APP_SPI_INTR_2_MAP_REG + const DPORT_APP_SPI_INTR_3_MAP_REG + const DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG + const DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG + const DPORT_APP_TG1_T0_EDGE_INT_MAP_REG + const DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG + const DPORT_APP_TG1_T1_EDGE_INT_MAP_REG + const DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG + const DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG + const DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG + const DPORT_APP_TG_LACT_EDGE_INT_MAP_REG + const DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG + const DPORT_APP_TG_T0_EDGE_INT_MAP_REG + const DPORT_APP_TG_T0_LEVEL_INT_MAP_REG + const DPORT_APP_TG_T1_EDGE_INT_MAP_REG + const DPORT_APP_TG_T1_LEVEL_INT_MAP_REG + const DPORT_APP_TG_WDT_EDGE_INT_MAP_REG + const DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG + const DPORT_APP_TIMER_INT1_MAP_REG + const DPORT_APP_TIMER_INT2_MAP_REG + const DPORT_APP_TWAI_INT_MAP_REG + const DPORT_APP_UART1_INTR_MAP_REG + const DPORT_APP_UART2_INTR_MAP_REG + const DPORT_APP_UART_INTR_MAP_REG + const DPORT_APP_UHCI0_INTR_MAP_REG + const DPORT_APP_UHCI1_INTR_MAP_REG + const DPORT_APP_WDG_INT_MAP_REG + const DPORT_CACHE_MUX_MODE_REG + const DPORT_CPU_INTR_FROM_CPU_0_REG + const DPORT_CPU_INTR_FROM_CPU_1_REG + const DPORT_CPU_INTR_FROM_CPU_2_REG + const DPORT_CPU_INTR_FROM_CPU_3_REG + const DPORT_CPU_PER_CONF_REG + const DPORT_DMMU_PAGE_MODE_REG + const DPORT_DMMU_TABLE0_REG + const DPORT_DMMU_TABLE10_REG + const DPORT_DMMU_TABLE11_REG + const DPORT_DMMU_TABLE12_REG + const DPORT_DMMU_TABLE13_REG + const DPORT_DMMU_TABLE14_REG + const DPORT_DMMU_TABLE15_REG + const DPORT_DMMU_TABLE1_REG + const DPORT_DMMU_TABLE2_REG + const DPORT_DMMU_TABLE3_REG + const DPORT_DMMU_TABLE4_REG + const DPORT_DMMU_TABLE5_REG + const DPORT_DMMU_TABLE6_REG + const DPORT_DMMU_TABLE7_REG + const DPORT_DMMU_TABLE8_REG + const DPORT_DMMU_TABLE9_REG + const DPORT_IMMU_PAGE_MODE_REG + const DPORT_IMMU_TABLE0_REG + const DPORT_IMMU_TABLE10_REG + const DPORT_IMMU_TABLE11_REG + const DPORT_IMMU_TABLE12_REG + const DPORT_IMMU_TABLE13_REG + const DPORT_IMMU_TABLE14_REG + const DPORT_IMMU_TABLE15_REG + const DPORT_IMMU_TABLE1_REG + const DPORT_IMMU_TABLE2_REG + const DPORT_IMMU_TABLE3_REG + const DPORT_IMMU_TABLE4_REG + const DPORT_IMMU_TABLE5_REG + const DPORT_IMMU_TABLE6_REG + const DPORT_IMMU_TABLE7_REG + const DPORT_IMMU_TABLE8_REG + const DPORT_IMMU_TABLE9_REG + const DPORT_PERIP_CLK_EN_REG + const DPORT_PERIP_RST_EN_REG + const DPORT_PERI_CLK_EN_REG + const DPORT_PERI_RST_EN_REG + const DPORT_PRO_BB_INT_MAP_REG + const DPORT_PRO_BOOT_REMAP_CTRL_REG + const DPORT_PRO_BT_BB_INT_MAP_REG + const DPORT_PRO_BT_BB_NMI_MAP_REG + const DPORT_PRO_BT_MAC_INT_MAP_REG + const DPORT_PRO_CACHE_CTRL1_REG + const DPORT_PRO_CACHE_CTRL_REG + const DPORT_PRO_CACHE_IA_INT_MAP_REG + const DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG + const DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG + const DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG + const DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG + const DPORT_PRO_EFUSE_INT_MAP_REG + const DPORT_PRO_EMAC_INT_MAP_REG + const DPORT_PRO_GPIO_INTERRUPT_MAP_REG + const DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG + const DPORT_PRO_I2C_EXT0_INTR_MAP_REG + const DPORT_PRO_I2C_EXT1_INTR_MAP_REG + const DPORT_PRO_I2S0_INT_MAP_REG + const DPORT_PRO_I2S1_INT_MAP_REG + const DPORT_PRO_INTR_STATUS_REG_0_REG + const DPORT_PRO_INTR_STATUS_REG_1_REG + const DPORT_PRO_INTR_STATUS_REG_2_REG + const DPORT_PRO_LEDC_INT_MAP_REG + const DPORT_PRO_MAC_INTR_MAP_REG + const DPORT_PRO_MAC_NMI_MAP_REG + const DPORT_PRO_MMU_IA_INT_MAP_REG + const DPORT_PRO_MPU_IA_INT_MAP_REG + const DPORT_PRO_PCNT_INTR_MAP_REG + const DPORT_PRO_PWM0_INTR_MAP_REG + const DPORT_PRO_PWM1_INTR_MAP_REG + const DPORT_PRO_RMT_INTR_MAP_REG + const DPORT_PRO_RSA_INTR_MAP_REG + const DPORT_PRO_RTC_CORE_INTR_MAP_REG + const DPORT_PRO_RWBLE_IRQ_MAP_REG + const DPORT_PRO_RWBLE_NMI_MAP_REG + const DPORT_PRO_RWBT_IRQ_MAP_REG + const DPORT_PRO_RWBT_NMI_MAP_REG + const DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG + const DPORT_PRO_SLC0_INTR_MAP_REG + const DPORT_PRO_SLC1_INTR_MAP_REG + const DPORT_PRO_SPI1_DMA_INT_MAP_REG + const DPORT_PRO_SPI2_DMA_INT_MAP_REG + const DPORT_PRO_SPI3_DMA_INT_MAP_REG + const DPORT_PRO_SPI_INTR_0_MAP_REG + const DPORT_PRO_SPI_INTR_1_MAP_REG + const DPORT_PRO_SPI_INTR_2_MAP_REG + const DPORT_PRO_SPI_INTR_3_MAP_REG + const DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG + const DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG + const DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG + const DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG + const DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG + const DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG + const DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG + const DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG + const DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG + const DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG + const DPORT_PRO_TG_T0_EDGE_INT_MAP_REG + const DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG + const DPORT_PRO_TG_T1_EDGE_INT_MAP_REG + const DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG + const DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG + const DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG + const DPORT_PRO_TIMER_INT1_MAP_REG + const DPORT_PRO_TIMER_INT2_MAP_REG + const DPORT_PRO_TWAI_INT_MAP_REG + const DPORT_PRO_UART1_INTR_MAP_REG + const DPORT_PRO_UART2_INTR_MAP_REG + const DPORT_PRO_UART_INTR_MAP_REG + const DPORT_PRO_UHCI0_INTR_MAP_REG + const DPORT_PRO_UHCI1_INTR_MAP_REG + const DPORT_PRO_WDG_INT_MAP_REG + const DPORT_SPI_DMA_CHAN_SEL_REG + const DPORT_WIFI_CLK_EN_REG + const DPORT_WIFI_RST_EN_REG + type PeripheralType byte + const AESAccelerator + const CacheMMUTable + const DPortRegister + const EFuseController + const EMAC + const FlashEncryption + const GPIO + const I2C0 + const I2C1 + const I2S0 + const I2S1 + const IOMUX + const LEDPWM + const MCPWM0 + const MCPWM1 + const PCNT + const PIDController + const RMT + const RNG + const RSAAccelerator + const RTC + const SDIOSlave1 + const SDIOSlave2 + const SDIOSlave3 + const SDMMC + const SHAAccelerator + const SPI0 + const SPI1 + const SPI2 + const SPI3 + const SYSCON + const SecureBoot + const TIMG0 + const TIMG1 + const TWAI + const UART0 + const UART1 + const UART2 + const UDMA0 + const UDMA1 + type SysConType byte + const SYSCON_APLL_TICK_CONF_REG + const SYSCON_CK8M_TICK_CONF_REG + const SYSCON_DATE_REG + const SYSCON_PLL_TICK_CONF_REG + const SYSCON_SYSCLK_CONF_REG + const SYSCON_XTAL_TICK_CONF_REG
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