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var ( AdrDPORT_PRO_BOOT_REMAP_CTRL_REG = AddressCellObj{AdrBeginDPORT_PRO_BOOT_REMAP_CTRL_REG, AdrEndDPORT_PRO_BOOT_REMAP_CTRL_REG} // R/W; remap mode for PRO_CPU AdrDPORT_APP_BOOT_REMAP_CTRL_REG = AddressCellObj{AdrBeginDPORT_APP_BOOT_REMAP_CTRL_REG, AdrEndDPORT_APP_BOOT_REMAP_CTRL_REG} // R/W; remap mode for APP_CPU AdrDPORT_CACHE_MUX_MODE_REG = AddressCellObj{AdrBeginDPORT_CACHE_MUX_MODE_REG, AdrEndDPORT_CACHE_MUX_MODE_REG} // R/W; the mode of the two caches sharing the memory AdrDPORT_CPU_PER_CONF_REG = AddressCellObj{AdrBeginDPORT_CPU_PER_CONF_REG, AdrEndDPORT_CPU_PER_CONF_REG} // R/W; Selects CPU clock AdrDPORT_CPU_INTR_FROM_CPU_0_REG = AddressCellObj{AdrBeginDPORT_CPU_INTR_FROM_CPU_0_REG, AdrEndDPORT_CPU_INTR_FROM_CPU_0_REG} // R/W; interrupt 0 in both CPUs AdrDPORT_CPU_INTR_FROM_CPU_1_REG = AddressCellObj{AdrBeginDPORT_CPU_INTR_FROM_CPU_1_REG, AdrEndDPORT_CPU_INTR_FROM_CPU_1_REG} // R/W; interrupt 1 in both CPUs AdrDPORT_CPU_INTR_FROM_CPU_2_REG = AddressCellObj{AdrBeginDPORT_CPU_INTR_FROM_CPU_2_REG, AdrEndDPORT_CPU_INTR_FROM_CPU_2_REG} // R/W; interrupt 2 in both CPUs AdrDPORT_CPU_INTR_FROM_CPU_3_REG = AddressCellObj{AdrBeginDPORT_CPU_INTR_FROM_CPU_3_REG, AdrEndDPORT_CPU_INTR_FROM_CPU_3_REG} // R/W; interrupt 3 in both CPUs AdrDPORT_PRO_INTR_STATUS_REG_0_REG = AddressCellObj{AdrBeginDPORT_PRO_INTR_STATUS_REG_0_REG, AdrEndDPORT_PRO_INTR_STATUS_REG_0_REG} // RO; PRO_CPU interrupt status 0 AdrDPORT_PRO_INTR_STATUS_REG_1_REG = AddressCellObj{AdrBeginDPORT_PRO_INTR_STATUS_REG_1_REG, AdrEndDPORT_PRO_INTR_STATUS_REG_1_REG} // RO; PRO_CPU interrupt status 1 AdrDPORT_PRO_INTR_STATUS_REG_2_REG = AddressCellObj{AdrBeginDPORT_PRO_INTR_STATUS_REG_2_REG, AdrEndDPORT_PRO_INTR_STATUS_REG_2_REG} // RO; PRO_CPU interrupt status 2 AdrDPORT_APP_INTR_STATUS_REG_0_REG = AddressCellObj{AdrBeginDPORT_APP_INTR_STATUS_REG_0_REG, AdrEndDPORT_APP_INTR_STATUS_REG_0_REG} // RO; APP_CPU interrupt status 0 AdrDPORT_APP_INTR_STATUS_REG_1_REG = AddressCellObj{AdrBeginDPORT_APP_INTR_STATUS_REG_1_REG, AdrEndDPORT_APP_INTR_STATUS_REG_1_REG} // RO; APP_CPU interrupt status 1 AdrDPORT_APP_INTR_STATUS_REG_2_REG = AddressCellObj{AdrBeginDPORT_APP_INTR_STATUS_REG_2_REG, AdrEndDPORT_APP_INTR_STATUS_REG_2_REG} // RO; APP_CPU interrupt status 2 AdrDPORT_PRO_MAC_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_MAC_INTR_MAP_REG, AdrEndDPORT_PRO_MAC_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_MAC_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_MAC_NMI_MAP_REG, AdrEndDPORT_PRO_MAC_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_BB_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_BB_INT_MAP_REG, AdrEndDPORT_PRO_BB_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_BT_MAC_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_BT_MAC_INT_MAP_REG, AdrEndDPORT_PRO_BT_MAC_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_BT_BB_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_BT_BB_INT_MAP_REG, AdrEndDPORT_PRO_BT_BB_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_BT_BB_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_BT_BB_NMI_MAP_REG, AdrEndDPORT_PRO_BT_BB_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_RWBT_IRQ_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_RWBT_IRQ_MAP_REG, AdrEndDPORT_PRO_RWBT_IRQ_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_RWBLE_IRQ_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_RWBLE_IRQ_MAP_REG, AdrEndDPORT_PRO_RWBLE_IRQ_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_RWBT_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_RWBT_NMI_MAP_REG, AdrEndDPORT_PRO_RWBT_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_RWBLE_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_RWBLE_NMI_MAP_REG, AdrEndDPORT_PRO_RWBLE_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SLC0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SLC0_INTR_MAP_REG, AdrEndDPORT_PRO_SLC0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SLC1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SLC1_INTR_MAP_REG, AdrEndDPORT_PRO_SLC1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_UHCI0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_UHCI0_INTR_MAP_REG, AdrEndDPORT_PRO_UHCI0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_UHCI1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_UHCI1_INTR_MAP_REG, AdrEndDPORT_PRO_UHCI1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG, AdrEndDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_GPIO_INTERRUPT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_GPIO_INTERRUPT_MAP_REG, AdrEndDPORT_PRO_GPIO_INTERRUPT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG, AdrEndDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG, AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG, AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG, AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG} // R/W; Interrupt map AdrDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG, AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SPI_INTR_0_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SPI_INTR_0_MAP_REG, AdrEndDPORT_PRO_SPI_INTR_0_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SPI_INTR_1_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SPI_INTR_1_MAP_REG, AdrEndDPORT_PRO_SPI_INTR_1_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SPI_INTR_2_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SPI_INTR_2_MAP_REG, AdrEndDPORT_PRO_SPI_INTR_2_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SPI_INTR_3_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SPI_INTR_3_MAP_REG, AdrEndDPORT_PRO_SPI_INTR_3_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_I2S0_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_I2S0_INT_MAP_REG, AdrEndDPORT_PRO_I2S0_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_I2S1_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_I2S1_INT_MAP_REG, AdrEndDPORT_PRO_I2S1_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_UART_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_UART_INTR_MAP_REG, AdrEndDPORT_PRO_UART_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_UART1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_UART1_INTR_MAP_REG, AdrEndDPORT_PRO_UART1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_UART2_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_UART2_INTR_MAP_REG, AdrEndDPORT_PRO_UART2_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG, AdrEndDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_EMAC_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_EMAC_INT_MAP_REG, AdrEndDPORT_PRO_EMAC_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_PWM0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_PWM0_INTR_MAP_REG, AdrEndDPORT_PRO_PWM0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_PWM1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_PWM1_INTR_MAP_REG, AdrEndDPORT_PRO_PWM1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_LEDC_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_LEDC_INT_MAP_REG, AdrEndDPORT_PRO_LEDC_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_EFUSE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_EFUSE_INT_MAP_REG, AdrEndDPORT_PRO_EFUSE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TWAI_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TWAI_INT_MAP_REG, AdrEndDPORT_PRO_TWAI_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_RTC_CORE_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_RTC_CORE_INTR_MAP_REG, AdrEndDPORT_PRO_RTC_CORE_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_RMT_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_RMT_INTR_MAP_REG, AdrEndDPORT_PRO_RMT_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_PCNT_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_PCNT_INTR_MAP_REG, AdrEndDPORT_PRO_PCNT_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_I2C_EXT0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_I2C_EXT0_INTR_MAP_REG, AdrEndDPORT_PRO_I2C_EXT0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_I2C_EXT1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_I2C_EXT1_INTR_MAP_REG, AdrEndDPORT_PRO_I2C_EXT1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_RSA_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_RSA_INTR_MAP_REG, AdrEndDPORT_PRO_RSA_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SPI1_DMA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SPI1_DMA_INT_MAP_REG, AdrEndDPORT_PRO_SPI1_DMA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SPI2_DMA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SPI2_DMA_INT_MAP_REG, AdrEndDPORT_PRO_SPI2_DMA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_SPI3_DMA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_SPI3_DMA_INT_MAP_REG, AdrEndDPORT_PRO_SPI3_DMA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_WDG_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_WDG_INT_MAP_REG, AdrEndDPORT_PRO_WDG_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TIMER_INT1_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TIMER_INT1_MAP_REG, AdrEndDPORT_PRO_TIMER_INT1_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TIMER_INT2_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TIMER_INT2_MAP_REG, AdrEndDPORT_PRO_TIMER_INT2_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_T0_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_T0_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG_T0_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_T1_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_T1_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG_T1_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG, AdrEndDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_MMU_IA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_MMU_IA_INT_MAP_REG, AdrEndDPORT_PRO_MMU_IA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_MPU_IA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_MPU_IA_INT_MAP_REG, AdrEndDPORT_PRO_MPU_IA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_PRO_CACHE_IA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_PRO_CACHE_IA_INT_MAP_REG, AdrEndDPORT_PRO_CACHE_IA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_MAC_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_MAC_INTR_MAP_REG, AdrEndDPORT_APP_MAC_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_MAC_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_MAC_NMI_MAP_REG, AdrEndDPORT_APP_MAC_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_APP_BB_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_BB_INT_MAP_REG, AdrEndDPORT_APP_BB_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_BT_MAC_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_BT_MAC_INT_MAP_REG, AdrEndDPORT_APP_BT_MAC_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_BT_BB_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_BT_BB_INT_MAP_REG, AdrEndDPORT_APP_BT_BB_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_BT_BB_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_BT_BB_NMI_MAP_REG, AdrEndDPORT_APP_BT_BB_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_APP_RWBT_IRQ_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_RWBT_IRQ_MAP_REG, AdrEndDPORT_APP_RWBT_IRQ_MAP_REG} // R/W; interrupt map AdrDPORT_APP_RWBLE_IRQ_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_RWBLE_IRQ_MAP_REG, AdrEndDPORT_APP_RWBLE_IRQ_MAP_REG} // R/W; interrupt map AdrDPORT_APP_RWBT_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_RWBT_NMI_MAP_REG, AdrEndDPORT_APP_RWBT_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_APP_RWBLE_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_RWBLE_NMI_MAP_REG, AdrEndDPORT_APP_RWBLE_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SLC0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SLC0_INTR_MAP_REG, AdrEndDPORT_APP_SLC0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SLC1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SLC1_INTR_MAP_REG, AdrEndDPORT_APP_SLC1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_UHCI0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_UHCI0_INTR_MAP_REG, AdrEndDPORT_APP_UHCI0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_UHCI1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_UHCI1_INTR_MAP_REG, AdrEndDPORT_APP_UHCI1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_T0_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_T0_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG_T0_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_T1_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_T1_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG_T1_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG, AdrEndDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_GPIO_INTERRUPT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_GPIO_INTERRUPT_MAP_REG, AdrEndDPORT_APP_GPIO_INTERRUPT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG, AdrEndDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG} // R/W; interrupt map AdrDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG, AdrEndDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG} // R/W; interrupt map AdrDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG, AdrEndDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG} // R/W; interrupt map AdrDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG, AdrEndDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG} // R/W; interrupt map AdrDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG, AdrEndDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SPI_INTR_0_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SPI_INTR_0_MAP_REG, AdrEndDPORT_APP_SPI_INTR_0_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SPI_INTR_1_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SPI_INTR_1_MAP_REG, AdrEndDPORT_APP_SPI_INTR_1_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SPI_INTR_2_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SPI_INTR_2_MAP_REG, AdrEndDPORT_APP_SPI_INTR_2_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SPI_INTR_3_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SPI_INTR_3_MAP_REG, AdrEndDPORT_APP_SPI_INTR_3_MAP_REG} // R/W; interrupt map AdrDPORT_APP_I2S0_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_I2S0_INT_MAP_REG, AdrEndDPORT_APP_I2S0_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_I2S1_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_I2S1_INT_MAP_REG, AdrEndDPORT_APP_I2S1_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_UART_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_UART_INTR_MAP_REG, AdrEndDPORT_APP_UART_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_UART1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_UART1_INTR_MAP_REG, AdrEndDPORT_APP_UART1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_UART2_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_UART2_INTR_MAP_REG, AdrEndDPORT_APP_UART2_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG, AdrEndDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_EMAC_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_EMAC_INT_MAP_REG, AdrEndDPORT_APP_EMAC_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_PWM0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_PWM0_INTR_MAP_REG, AdrEndDPORT_APP_PWM0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_PWM1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_PWM1_INTR_MAP_REG, AdrEndDPORT_APP_PWM1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_LEDC_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_LEDC_INT_MAP_REG, AdrEndDPORT_APP_LEDC_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_EFUSE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_EFUSE_INT_MAP_REG, AdrEndDPORT_APP_EFUSE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TWAI_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TWAI_INT_MAP_REG, AdrEndDPORT_APP_TWAI_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_RTC_CORE_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_RTC_CORE_INTR_MAP_REG, AdrEndDPORT_APP_RTC_CORE_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_RMT_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_RMT_INTR_MAP_REG, AdrEndDPORT_APP_RMT_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_PCNT_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_PCNT_INTR_MAP_REG, AdrEndDPORT_APP_PCNT_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_I2C_EXT0_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_I2C_EXT0_INTR_MAP_REG, AdrEndDPORT_APP_I2C_EXT0_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_I2C_EXT1_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_I2C_EXT1_INTR_MAP_REG, AdrEndDPORT_APP_I2C_EXT1_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_RSA_INTR_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_RSA_INTR_MAP_REG, AdrEndDPORT_APP_RSA_INTR_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SPI1_DMA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SPI1_DMA_INT_MAP_REG, AdrEndDPORT_APP_SPI1_DMA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SPI2_DMA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SPI2_DMA_INT_MAP_REG, AdrEndDPORT_APP_SPI2_DMA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_SPI3_DMA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_SPI3_DMA_INT_MAP_REG, AdrEndDPORT_APP_SPI3_DMA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_WDG_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_WDG_INT_MAP_REG, AdrEndDPORT_APP_WDG_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TIMER_INT1_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TIMER_INT1_MAP_REG, AdrEndDPORT_APP_TIMER_INT1_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TIMER_INT2_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TIMER_INT2_MAP_REG, AdrEndDPORT_APP_TIMER_INT2_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_T0_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_T0_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG_T0_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_T1_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_T1_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG_T1_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_WDT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_WDT_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG_WDT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG_LACT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG_LACT_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG_LACT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_T0_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_T0_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG1_T0_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_T1_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_T1_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG1_T1_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG, AdrEndDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_MMU_IA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_MMU_IA_INT_MAP_REG, AdrEndDPORT_APP_MMU_IA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_MPU_IA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_MPU_IA_INT_MAP_REG, AdrEndDPORT_APP_MPU_IA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_APP_CACHE_IA_INT_MAP_REG = AddressCellObj{AdrBeginDPORT_APP_CACHE_IA_INT_MAP_REG, AdrEndDPORT_APP_CACHE_IA_INT_MAP_REG} // R/W; interrupt map AdrDPORT_SPI_DMA_CHAN_SEL_REG = AddressCellObj{AdrBeginDPORT_SPI_DMA_CHAN_SEL_REG, AdrEndDPORT_SPI_DMA_CHAN_SEL_REG} // R/W; selects DMA channel for SPI1 and SPI2 and SPI3 AdrDPORT_PRO_CACHE_CTRL_REG = AddressCellObj{AdrBeginDPORT_PRO_CACHE_CTRL_REG, AdrEndDPORT_PRO_CACHE_CTRL_REG} // R/W; determines the virtual address mode of the external SRAM AdrDPORT_PRO_CACHE_CTRL1_REG = AddressCellObj{AdrBeginDPORT_PRO_CACHE_CTRL1_REG, AdrEndDPORT_PRO_CACHE_CTRL1_REG} // R/W; PRO cache MMU configuration AdrDPORT_APP_CACHE_CTRL_REG = AddressCellObj{AdrBeginDPORT_APP_CACHE_CTRL_REG, AdrEndDPORT_APP_CACHE_CTRL_REG} // R/W; determines the virtual address mode of the external SRAM AdrDPORT_APP_CACHE_CTRL1_REG = AddressCellObj{AdrBeginDPORT_APP_CACHE_CTRL1_REG, AdrEndDPORT_APP_CACHE_CTRL1_REG} // R/W; APP cache MMU configuration AdrDPORT_IMMU_PAGE_MODE_REG = AddressCellObj{AdrBeginDPORT_IMMU_PAGE_MODE_REG, AdrEndDPORT_IMMU_PAGE_MODE_REG} // R/W; page size in the MMU for the internal SRAM 0 AdrDPORT_DMMU_PAGE_MODE_REG = AddressCellObj{AdrBeginDPORT_DMMU_PAGE_MODE_REG, AdrEndDPORT_DMMU_PAGE_MODE_REG} // R/W; page size in the MMU for the internal SRAM 2 AdrDPORT_AHB_MPU_TABLE_0_REG = AddressCellObj{AdrBeginDPORT_AHB_MPU_TABLE_0_REG, AdrEndDPORT_AHB_MPU_TABLE_0_REG} // R/W; MPU for configuring DMA AdrDPORT_AHB_MPU_TABLE_1_REG = AddressCellObj{AdrBeginDPORT_AHB_MPU_TABLE_1_REG, AdrEndDPORT_AHB_MPU_TABLE_1_REG} // R/W; MPU for configuring DMA AdrDPORT_AHBLITE_MPU_TABLE_UART_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_UART_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_UART_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SPI1_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI1_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SPI1_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SPI0_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI0_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SPI0_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_GPIO_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_GPIO_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_GPIO_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_RTC_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_RTC_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_RTC_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_HINF_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_HINF_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_HINF_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_UHCI1_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_UHCI1_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_UHCI1_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_I2S0_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_I2S0_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_I2S0_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_UART1_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_UART1_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_UART1_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_UHCI0_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_UHCI0_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_UHCI0_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_RMT_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_RMT_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_RMT_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_PCNT_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_PCNT_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_PCNT_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SLC_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SLC_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SLC_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_LEDC_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_LEDC_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_LEDC_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_EFUSE_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_EFUSE_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_EFUSE_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_PWM0_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_PWM0_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_PWM0_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SPI2_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI2_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SPI2_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SPI3_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI3_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SPI3_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_EMAC_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_EMAC_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_EMAC_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_PWM1_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_PWM1_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_PWM1_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_I2S1_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_I2S1_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_I2S1_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_UART2_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_UART2_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_UART2_REG} // R/W; MPU for peripherals AdrDPORT_AHBLITE_MPU_TABLE_PWR_REG = AddressCellObj{AdrBeginDPORT_AHBLITE_MPU_TABLE_PWR_REG, AdrEndDPORT_AHBLITE_MPU_TABLE_PWR_REG} // R/W; MPU for peripherals AdrDPORT_IMMU_TABLE0_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE0_REG, AdrEndDPORT_IMMU_TABLE0_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE1_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE1_REG, AdrEndDPORT_IMMU_TABLE1_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE2_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE2_REG, AdrEndDPORT_IMMU_TABLE2_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE3_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE3_REG, AdrEndDPORT_IMMU_TABLE3_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE4_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE4_REG, AdrEndDPORT_IMMU_TABLE4_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE5_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE5_REG, AdrEndDPORT_IMMU_TABLE5_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE6_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE6_REG, AdrEndDPORT_IMMU_TABLE6_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE7_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE7_REG, AdrEndDPORT_IMMU_TABLE7_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE8_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE8_REG, AdrEndDPORT_IMMU_TABLE8_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE9_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE9_REG, AdrEndDPORT_IMMU_TABLE9_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE10_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE10_REG, AdrEndDPORT_IMMU_TABLE10_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE11_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE11_REG, AdrEndDPORT_IMMU_TABLE11_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE12_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE12_REG, AdrEndDPORT_IMMU_TABLE12_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE13_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE13_REG, AdrEndDPORT_IMMU_TABLE13_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE14_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE14_REG, AdrEndDPORT_IMMU_TABLE14_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_IMMU_TABLE15_REG = AddressCellObj{AdrBeginDPORT_IMMU_TABLE15_REG, AdrEndDPORT_IMMU_TABLE15_REG} // R/W; MMU register 1 for internal SRAM 0 AdrDPORT_DMMU_TABLE0_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE0_REG, AdrEndDPORT_DMMU_TABLE0_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE1_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE1_REG, AdrEndDPORT_DMMU_TABLE1_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE2_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE2_REG, AdrEndDPORT_DMMU_TABLE2_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE3_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE3_REG, AdrEndDPORT_DMMU_TABLE3_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE4_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE4_REG, AdrEndDPORT_DMMU_TABLE4_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE5_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE5_REG, AdrEndDPORT_DMMU_TABLE5_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE6_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE6_REG, AdrEndDPORT_DMMU_TABLE6_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE7_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE7_REG, AdrEndDPORT_DMMU_TABLE7_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE8_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE8_REG, AdrEndDPORT_DMMU_TABLE8_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE9_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE9_REG, AdrEndDPORT_DMMU_TABLE9_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE10_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE10_REG, AdrEndDPORT_DMMU_TABLE10_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE11_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE11_REG, AdrEndDPORT_DMMU_TABLE11_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE12_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE12_REG, AdrEndDPORT_DMMU_TABLE12_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE13_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE13_REG, AdrEndDPORT_DMMU_TABLE13_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE14_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE14_REG, AdrEndDPORT_DMMU_TABLE14_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_DMMU_TABLE15_REG = AddressCellObj{AdrBeginDPORT_DMMU_TABLE15_REG, AdrEndDPORT_DMMU_TABLE15_REG} // R/W; MMU register 1 for internal SRAM 2 AdrDPORT_APPCPU_CTRL_REG_A_REG = AddressCellObj{AdrBeginDPORT_APPCPU_CTRL_REG_A_REG, AdrEndDPORT_APPCPU_CTRL_REG_A_REG} // R/W; reset for APP_CPU AdrDPORT_APPCPU_CTRL_REG_B_REG = AddressCellObj{AdrBeginDPORT_APPCPU_CTRL_REG_B_REG, AdrEndDPORT_APPCPU_CTRL_REG_B_REG} // R/W; clock gate for APP_CPU AdrDPORT_APPCPU_CTRL_REG_C_REG = AddressCellObj{AdrBeginDPORT_APPCPU_CTRL_REG_C_REG, AdrEndDPORT_APPCPU_CTRL_REG_C_REG} // R/W; stall for APP_CPU AdrDPORT_APPCPU_CTRL_REG_D_REG = AddressCellObj{AdrBeginDPORT_APPCPU_CTRL_REG_D_REG, AdrEndDPORT_APPCPU_CTRL_REG_D_REG} // R/W; boot address for APP_CPU AdrDPORT_PERI_CLK_EN_REG = AddressCellObj{AdrBeginDPORT_PERI_CLK_EN_REG, AdrEndDPORT_PERI_CLK_EN_REG} // R/W; clock gate for peripherals AdrDPORT_PERI_RST_EN_REG = AddressCellObj{AdrBeginDPORT_PERI_RST_EN_REG, AdrEndDPORT_PERI_RST_EN_REG} // R/W; reset for peripherals AdrDPORT_PERIP_CLK_EN_REG = AddressCellObj{AdrBeginDPORT_PERIP_CLK_EN_REG, AdrEndDPORT_PERIP_CLK_EN_REG} // R/W; clock gate for peripherals AdrDPORT_PERIP_RST_EN_REG = AddressCellObj{AdrBeginDPORT_PERIP_RST_EN_REG, AdrEndDPORT_PERIP_RST_EN_REG} // R/W; reset for peripherals AdrDPORT_WIFI_CLK_EN_REG = AddressCellObj{AdrBeginDPORT_WIFI_CLK_EN_REG, AdrEndDPORT_WIFI_CLK_EN_REG} // R/W; clock gate for Wi-Fi AdrDPORT_WIFI_RST_EN_REG = AddressCellObj{AdrBeginDPORT_WIFI_RST_EN_REG, AdrEndDPORT_WIFI_RST_EN_REG} // R/W; reset for Wi-Fi )
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var ( AdrSYSCON_SYSCLK_CONF_REG = AddressCellObj{AdrBeginSYSCON_SYSCLK_CONF_REG, AdrEndSYSCON_SYSCLK_CONF_REG} // R/W; Configures system clock frequency AdrSYSCON_XTAL_TICK_CONF_REG = AddressCellObj{AdrBeginSYSCON_XTAL_TICK_CONF_REG, AdrEndSYSCON_XTAL_TICK_CONF_REG} // R/W; Configures the divider value of REF_TICK AdrSYSCON_PLL_TICK_CONF_REG = AddressCellObj{AdrBeginSYSCON_PLL_TICK_CONF_REG, AdrEndSYSCON_PLL_TICK_CONF_REG} // R/W; Configures the divider value of REF_TICK AdrSYSCON_CK8M_TICK_CONF_REG = AddressCellObj{AdrBeginSYSCON_CK8M_TICK_CONF_REG, AdrEndSYSCON_CK8M_TICK_CONF_REG} // R/W; Configures the divider value of REF_TICK AdrSYSCON_APLL_TICK_CONF_REG = AddressCellObj{AdrBeginSYSCON_APLL_TICK_CONF_REG, AdrEndSYSCON_APLL_TICK_CONF_REG} // R/W; Configures the divider value of REF_TICK AdrSYSCON_DATE_REG = AddressCellObj{AdrBeginSYSCON_DATE_REG, AdrEndSYSCON_DATE_REG} // R/W; Chip revision register )
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var ( AdrDPortRegister = AddressCellObj{AdrBeginDPortRegister, AdrEndDPortRegister} //4 KB AdrAESAccelerator = AddressCellObj{AdrBeginAESAccelerator, AdrEndAESAccelerator} //4 KB AdrRSAAccelerator = AddressCellObj{AdrBeginRSAAccelerator, AdrEndRSAAccelerator} //4 KB AdrSHAAccelerator = AddressCellObj{AdrBeginSHAAccelerator, AdrEndSHAAccelerator} //4 KB AdrSecureBoot = AddressCellObj{AdrBeginSecureBoot, AdrEndSecureBoot} //4 KB AdrCacheMMUTable = AddressCellObj{AdrBeginCacheMMUTable, AdrEndCacheMMUTable} //16 KB AdrPIDController = AddressCellObj{AdrBeginPIDController, AdrEndPIDController} //4 KB Per-CPU peripheral AdrUART0 = AddressCellObj{AdrBeginUART0, AdrEndUART0} //4 KB AdrSPI1 = AddressCellObj{AdrBeginSPI1, AdrEndSPI1} //4 KB AdrSPI0 = AddressCellObj{AdrBeginSPI0, AdrEndSPI0} //4 KB AdrGPIO = AddressCellObj{AdrBeginGPIO, AdrEndGPIO} //4 KB AdrRTC = AddressCellObj{AdrBeginRTC, AdrEndRTC} //4 KB AdrIOMUX = AddressCellObj{AdrBeginIOMUX, AdrEndIOMUX} //4 KB AdrSDIOSlave1 = AddressCellObj{AdrBeginSDIOSlave1, AdrEndSDIOSlave1} //4 KB One of three parts AdrUDMA1 = AddressCellObj{AdrBeginUDMA1, AdrEndUDMA1} //4 KB AdrI2S0 = AddressCellObj{AdrBeginI2S0, AdrEndI2S0} //4 KB AdrUART1 = AddressCellObj{AdrBeginUART1, AdrEndUART1} //4 KB AdrI2C0 = AddressCellObj{AdrBeginI2C0, AdrEndI2C0} //4 KB AdrUDMA0 = AddressCellObj{AdrBeginUDMA0, AdrEndUDMA0} //4 KB AdrSDIOSlave2 = AddressCellObj{AdrBeginSDIOSlave2, AdrEndSDIOSlave2} //4 KB One of three parts AdrRMT = AddressCellObj{AdrBeginRMT, AdrEndRMT} //4 KB AdrPCNT = AddressCellObj{AdrBeginPCNT, AdrEndPCNT} //4 KB AdrSDIOSlave3 = AddressCellObj{AdrBeginSDIOSlave3, AdrEndSDIOSlave3} //4 KB One of three parts AdrLEDPWM = AddressCellObj{AdrBeginLEDPWM, AdrEndLEDPWM} //4 KB AdrEFuseController = AddressCellObj{AdrBeginEFuseController, AdrEndEFuseController} //4 KB AdrFlashEncryption = AddressCellObj{AdrBeginFlashEncryption, AdrEndFlashEncryption} //4 KB AdrMCPWM0 = AddressCellObj{AdrBeginMCPWM0, AdrEndMCPWM0} //4 KB AdrTIMG0 = AddressCellObj{AdrBeginTIMG0, AdrEndTIMG0} //4 KB AdrTIMG1 = AddressCellObj{AdrBeginTIMG1, AdrEndTIMG1} //4 KB AdrSPI2 = AddressCellObj{AdrBeginSPI2, AdrEndSPI2} //4 KB AdrSPI3 = AddressCellObj{AdrBeginSPI3, AdrEndSPI3} //4 KB AdrSYSCON = AddressCellObj{AdrBeginSYSCON, AdrEndSYSCON} //4 KB AdrI2C1 = AddressCellObj{AdrBeginI2C1, AdrEndI2C1} //4 KB AdrSDMMC = AddressCellObj{AdrBeginSDMMC, AdrEndSDMMC} //4 KB AdrEMAC = AddressCellObj{AdrBeginEMAC, AdrEndEMAC} //8 KB AdrTWAI = AddressCellObj{AdrBeginTWAI, AdrEndTWAI} //4KB AdrMCPWM1 = AddressCellObj{AdrBeginMCPWM1, AdrEndMCPWM1} //4 KB AdrI2S1 = AddressCellObj{AdrBeginI2S1, AdrEndI2S1} //4 KB AdrUART2 = AddressCellObj{AdrBeginUART2, AdrEndUART2} //4 KB AdrRNG = AddressCellObj{AdrBeginRNG, AdrEndRNG} //4 KB )
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var DPortMap = map[DPortType]*AddressCellObj{}/* 231 elements not displayed */
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var PeripheralMap = map[PeripheralType]*AddressCellObj{ DPortRegister: &AdrDPortRegister, AESAccelerator: &AdrAESAccelerator, RSAAccelerator: &AdrRSAAccelerator, SHAAccelerator: &AdrSHAAccelerator, SecureBoot: &AdrSecureBoot, CacheMMUTable: &AdrCacheMMUTable, PIDController: &AdrPIDController, UART0: &AdrUART0, SPI1: &AdrSPI1, SPI0: &AdrSPI0, GPIO: &AdrGPIO, RTC: &AdrRTC, IOMUX: &AdrIOMUX, SDIOSlave1: &AdrSDIOSlave1, UDMA1: &AdrUDMA1, I2S0: &AdrI2S0, UART1: &AdrUART1, I2C0: &AdrI2C0, UDMA0: &AdrUDMA0, SDIOSlave2: &AdrSDIOSlave2, RMT: &AdrRMT, PCNT: &AdrPCNT, SDIOSlave3: &AdrSDIOSlave3, LEDPWM: &AdrLEDPWM, EFuseController: &AdrEFuseController, FlashEncryption: &AdrFlashEncryption, MCPWM0: &AdrMCPWM0, TIMG0: &AdrTIMG0, TIMG1: &AdrTIMG1, SPI2: &AdrSPI2, SPI3: &AdrSPI3, SYSCON: &AdrSYSCON, I2C1: &AdrI2C1, SDMMC: &AdrSDMMC, EMAC: &AdrEMAC, TWAI: &AdrTWAI, MCPWM1: &AdrMCPWM1, I2S1: &AdrI2S1, UART2: &AdrUART2, RNG: &AdrRNG, }
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var SysConMap = map[SysConType]*AddressCellObj{ SYSCON_SYSCLK_CONF_REG: &AdrSYSCON_SYSCLK_CONF_REG, SYSCON_XTAL_TICK_CONF_REG: &AdrSYSCON_XTAL_TICK_CONF_REG, SYSCON_PLL_TICK_CONF_REG: &AdrSYSCON_PLL_TICK_CONF_REG, SYSCON_CK8M_TICK_CONF_REG: &AdrSYSCON_CK8M_TICK_CONF_REG, SYSCON_APLL_TICK_CONF_REG: &AdrSYSCON_APLL_TICK_CONF_REG, SYSCON_DATE_REG: &AdrSYSCON_DATE_REG, }
Functions ¶
This section is empty.
Types ¶
type AddressCellObj ¶
type AddressCellObj struct {
Begin AddressType
End AddressType
}
func (*AddressCellObj) Size ¶
func (adr *AddressCellObj) Size() AddressType
type AddressType ¶
type AddressType uint64
const ( AdrBeginDPORT_PRO_BOOT_REMAP_CTRL_REG AddressType = 0x3FF00000 AdrBeginDPORT_APP_BOOT_REMAP_CTRL_REG AddressType = 0x3FF00004 AdrBeginDPORT_CACHE_MUX_MODE_REG AddressType = 0x3FF0007C AdrBeginDPORT_CPU_PER_CONF_REG AddressType = 0x3FF0003C AdrBeginDPORT_CPU_INTR_FROM_CPU_0_REG AddressType = 0x3FF000DC AdrBeginDPORT_CPU_INTR_FROM_CPU_1_REG AddressType = 0x3FF000E0 AdrBeginDPORT_CPU_INTR_FROM_CPU_2_REG AddressType = 0x3FF000E4 AdrBeginDPORT_CPU_INTR_FROM_CPU_3_REG AddressType = 0x3FF000E8 AdrBeginDPORT_PRO_INTR_STATUS_REG_0_REG AddressType = 0x3FF000EC AdrBeginDPORT_PRO_INTR_STATUS_REG_1_REG AddressType = 0x3FF000F0 AdrBeginDPORT_PRO_INTR_STATUS_REG_2_REG AddressType = 0x3FF000F4 AdrBeginDPORT_APP_INTR_STATUS_REG_0_REG AddressType = 0x3FF000F8 AdrBeginDPORT_APP_INTR_STATUS_REG_1_REG AddressType = 0x3FF000FC AdrBeginDPORT_APP_INTR_STATUS_REG_2_REG AddressType = 0x3FF00100 AdrBeginDPORT_PRO_MAC_INTR_MAP_REG AddressType = 0x3FF00104 AdrBeginDPORT_PRO_MAC_NMI_MAP_REG AddressType = 0x3FF00108 AdrBeginDPORT_PRO_BB_INT_MAP_REG AddressType = 0x3FF0010C AdrBeginDPORT_PRO_BT_MAC_INT_MAP_REG AddressType = 0x3FF00110 AdrBeginDPORT_PRO_BT_BB_INT_MAP_REG AddressType = 0x3FF00114 AdrBeginDPORT_PRO_BT_BB_NMI_MAP_REG AddressType = 0x3FF00118 AdrBeginDPORT_PRO_RWBT_IRQ_MAP_REG AddressType = 0x3FF0011C AdrBeginDPORT_PRO_RWBLE_IRQ_MAP_REG AddressType = 0x3FF00120 AdrBeginDPORT_PRO_RWBT_NMI_MAP_REG AddressType = 0x3FF00124 AdrBeginDPORT_PRO_RWBLE_NMI_MAP_REG AddressType = 0x3FF00128 AdrBeginDPORT_PRO_SLC0_INTR_MAP_REG AddressType = 0x3FF0012C AdrBeginDPORT_PRO_SLC1_INTR_MAP_REG AddressType = 0x3FF00130 AdrBeginDPORT_PRO_UHCI0_INTR_MAP_REG AddressType = 0x3FF00134 AdrBeginDPORT_PRO_UHCI1_INTR_MAP_REG AddressType = 0x3FF00138 AdrBeginDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF0013C AdrBeginDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00140 AdrBeginDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF00144 AdrBeginDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF00148 AdrBeginDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF0014C AdrBeginDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00150 AdrBeginDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF00154 AdrBeginDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF00158 AdrBeginDPORT_PRO_GPIO_INTERRUPT_MAP_REG AddressType = 0x3FF0015C AdrBeginDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG AddressType = 0x3FF00160 AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG AddressType = 0x3FF00164 AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG AddressType = 0x3FF00168 AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG AddressType = 0x3FF0016C AdrBeginDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG AddressType = 0x3FF00170 AdrBeginDPORT_PRO_SPI_INTR_0_MAP_REG AddressType = 0x3FF00174 AdrBeginDPORT_PRO_SPI_INTR_1_MAP_REG AddressType = 0x3FF00178 AdrBeginDPORT_PRO_SPI_INTR_2_MAP_REG AddressType = 0x3FF0017C AdrBeginDPORT_PRO_SPI_INTR_3_MAP_REG AddressType = 0x3FF00180 AdrBeginDPORT_PRO_I2S0_INT_MAP_REG AddressType = 0x3FF00184 AdrBeginDPORT_PRO_I2S1_INT_MAP_REG AddressType = 0x3FF00188 AdrBeginDPORT_PRO_UART_INTR_MAP_REG AddressType = 0x3FF0018C AdrBeginDPORT_PRO_UART1_INTR_MAP_REG AddressType = 0x3FF00190 AdrBeginDPORT_PRO_UART2_INTR_MAP_REG AddressType = 0x3FF00194 AdrBeginDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG AddressType = 0x3FF00198 AdrBeginDPORT_PRO_EMAC_INT_MAP_REG AddressType = 0x3FF0019C AdrBeginDPORT_PRO_PWM0_INTR_MAP_REG AddressType = 0x3FF001A0 AdrBeginDPORT_PRO_PWM1_INTR_MAP_REG AddressType = 0x3FF001A4 AdrBeginDPORT_PRO_LEDC_INT_MAP_REG AddressType = 0x3FF001B0 AdrBeginDPORT_PRO_EFUSE_INT_MAP_REG AddressType = 0x3FF001B4 AdrBeginDPORT_PRO_TWAI_INT_MAP_REG AddressType = 0x3FF001B8 AdrBeginDPORT_PRO_RTC_CORE_INTR_MAP_REG AddressType = 0x3FF001BC AdrBeginDPORT_PRO_RMT_INTR_MAP_REG AddressType = 0x3FF001C0 AdrBeginDPORT_PRO_PCNT_INTR_MAP_REG AddressType = 0x3FF001C4 AdrBeginDPORT_PRO_I2C_EXT0_INTR_MAP_REG AddressType = 0x3FF001C8 AdrBeginDPORT_PRO_I2C_EXT1_INTR_MAP_REG AddressType = 0x3FF001CC AdrBeginDPORT_PRO_RSA_INTR_MAP_REG AddressType = 0x3FF001D0 AdrBeginDPORT_PRO_SPI1_DMA_INT_MAP_REG AddressType = 0x3FF001D4 AdrBeginDPORT_PRO_SPI2_DMA_INT_MAP_REG AddressType = 0x3FF001D8 AdrBeginDPORT_PRO_SPI3_DMA_INT_MAP_REG AddressType = 0x3FF001DC AdrBeginDPORT_PRO_WDG_INT_MAP_REG AddressType = 0x3FF001E0 AdrBeginDPORT_PRO_TIMER_INT1_MAP_REG AddressType = 0x3FF001E4 AdrBeginDPORT_PRO_TIMER_INT2_MAP_REG AddressType = 0x3FF001E8 AdrBeginDPORT_PRO_TG_T0_EDGE_INT_MAP_REG AddressType = 0x3FF001EC AdrBeginDPORT_PRO_TG_T1_EDGE_INT_MAP_REG AddressType = 0x3FF001F0 AdrBeginDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF001F4 AdrBeginDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF001F8 AdrBeginDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG AddressType = 0x3FF001FC AdrBeginDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG AddressType = 0x3FF00200 AdrBeginDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF00204 AdrBeginDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF00208 AdrBeginDPORT_PRO_MMU_IA_INT_MAP_REG AddressType = 0x3FF0020C AdrBeginDPORT_PRO_MPU_IA_INT_MAP_REG AddressType = 0x3FF00210 AdrBeginDPORT_PRO_CACHE_IA_INT_MAP_REG AddressType = 0x3FF00214 AdrBeginDPORT_APP_MAC_INTR_MAP_REG AddressType = 0x3FF00218 AdrBeginDPORT_APP_MAC_NMI_MAP_REG AddressType = 0x3FF0021C AdrBeginDPORT_APP_BB_INT_MAP_REG AddressType = 0x3FF00220 AdrBeginDPORT_APP_BT_MAC_INT_MAP_REG AddressType = 0x3FF00224 AdrBeginDPORT_APP_BT_BB_INT_MAP_REG AddressType = 0x3FF00228 AdrBeginDPORT_APP_BT_BB_NMI_MAP_REG AddressType = 0x3FF0022C AdrBeginDPORT_APP_RWBT_IRQ_MAP_REG AddressType = 0x3FF00230 AdrBeginDPORT_APP_RWBLE_IRQ_MAP_REG AddressType = 0x3FF00234 AdrBeginDPORT_APP_RWBT_NMI_MAP_REG AddressType = 0x3FF00238 AdrBeginDPORT_APP_RWBLE_NMI_MAP_REG AddressType = 0x3FF0023C AdrBeginDPORT_APP_SLC0_INTR_MAP_REG AddressType = 0x3FF00240 AdrBeginDPORT_APP_SLC1_INTR_MAP_REG AddressType = 0x3FF00244 AdrBeginDPORT_APP_UHCI0_INTR_MAP_REG AddressType = 0x3FF00248 AdrBeginDPORT_APP_UHCI1_INTR_MAP_REG AddressType = 0x3FF0024C AdrBeginDPORT_APP_TG_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF00250 AdrBeginDPORT_APP_TG_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00254 AdrBeginDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF00258 AdrBeginDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF0025C AdrBeginDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF00260 AdrBeginDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00264 AdrBeginDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF00268 AdrBeginDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF0026C AdrBeginDPORT_APP_GPIO_INTERRUPT_MAP_REG AddressType = 0x3FF00270 AdrBeginDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG AddressType = 0x3FF00274 AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG AddressType = 0x3FF00278 AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG AddressType = 0x3FF0027C AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG AddressType = 0x3FF00280 AdrBeginDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG AddressType = 0x3FF00284 AdrBeginDPORT_APP_SPI_INTR_0_MAP_REG AddressType = 0x3FF00288 AdrBeginDPORT_APP_SPI_INTR_1_MAP_REG AddressType = 0x3FF0028C AdrBeginDPORT_APP_SPI_INTR_2_MAP_REG AddressType = 0x3FF00290 AdrBeginDPORT_APP_SPI_INTR_3_MAP_REG AddressType = 0x3FF00294 AdrBeginDPORT_APP_I2S0_INT_MAP_REG AddressType = 0x3FF00298 AdrBeginDPORT_APP_I2S1_INT_MAP_REG AddressType = 0x3FF0029C AdrBeginDPORT_APP_UART_INTR_MAP_REG AddressType = 0x3FF002A0 AdrBeginDPORT_APP_UART1_INTR_MAP_REG AddressType = 0x3FF002A4 AdrBeginDPORT_APP_UART2_INTR_MAP_REG AddressType = 0x3FF002A8 AdrBeginDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG AddressType = 0x3FF002AC AdrBeginDPORT_APP_EMAC_INT_MAP_REG AddressType = 0x3FF002B0 AdrBeginDPORT_APP_PWM0_INTR_MAP_REG AddressType = 0x3FF002B4 AdrBeginDPORT_APP_PWM1_INTR_MAP_REG AddressType = 0x3FF002B8 AdrBeginDPORT_APP_LEDC_INT_MAP_REG AddressType = 0x3FF002C4 AdrBeginDPORT_APP_EFUSE_INT_MAP_REG AddressType = 0x3FF002C8 AdrBeginDPORT_APP_TWAI_INT_MAP_REG AddressType = 0x3FF002CC AdrBeginDPORT_APP_RTC_CORE_INTR_MAP_REG AddressType = 0x3FF002D0 AdrBeginDPORT_APP_RMT_INTR_MAP_REG AddressType = 0x3FF002D4 AdrBeginDPORT_APP_PCNT_INTR_MAP_REG AddressType = 0x3FF002D8 AdrBeginDPORT_APP_I2C_EXT0_INTR_MAP_REG AddressType = 0x3FF002DC AdrBeginDPORT_APP_I2C_EXT1_INTR_MAP_REG AddressType = 0x3FF002E0 AdrBeginDPORT_APP_RSA_INTR_MAP_REG AddressType = 0x3FF002E4 AdrBeginDPORT_APP_SPI1_DMA_INT_MAP_REG AddressType = 0x3FF002E8 AdrBeginDPORT_APP_SPI2_DMA_INT_MAP_REG AddressType = 0x3FF002EC AdrBeginDPORT_APP_SPI3_DMA_INT_MAP_REG AddressType = 0x3FF002F0 AdrBeginDPORT_APP_WDG_INT_MAP_REG AddressType = 0x3FF002F4 AdrBeginDPORT_APP_TIMER_INT1_MAP_REG AddressType = 0x3FF002F8 AdrBeginDPORT_APP_TIMER_INT2_MAP_REG AddressType = 0x3FF002FC AdrBeginDPORT_APP_TG_T0_EDGE_INT_MAP_REG AddressType = 0x3FF00300 AdrBeginDPORT_APP_TG_T1_EDGE_INT_MAP_REG AddressType = 0x3FF00304 AdrBeginDPORT_APP_TG_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF00308 AdrBeginDPORT_APP_TG_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF0030C AdrBeginDPORT_APP_TG1_T0_EDGE_INT_MAP_REG AddressType = 0x3FF00310 AdrBeginDPORT_APP_TG1_T1_EDGE_INT_MAP_REG AddressType = 0x3FF00314 AdrBeginDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF00318 AdrBeginDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF0031C AdrBeginDPORT_APP_MMU_IA_INT_MAP_REG AddressType = 0x3FF00320 AdrBeginDPORT_APP_MPU_IA_INT_MAP_REG AddressType = 0x3FF00324 AdrBeginDPORT_APP_CACHE_IA_INT_MAP_REG AddressType = 0x3FF00328 AdrBeginDPORT_SPI_DMA_CHAN_SEL_REG AddressType = 0x3FF005A8 AdrBeginDPORT_PRO_CACHE_CTRL_REG AddressType = 0x3FF00040 AdrBeginDPORT_PRO_CACHE_CTRL1_REG AddressType = 0x3FF00044 AdrBeginDPORT_APP_CACHE_CTRL_REG AddressType = 0x3FF00058 AdrBeginDPORT_APP_CACHE_CTRL1_REG AddressType = 0x3FF0005C AdrBeginDPORT_IMMU_PAGE_MODE_REG AddressType = 0x3FF00080 AdrBeginDPORT_DMMU_PAGE_MODE_REG AddressType = 0x3FF00084 AdrBeginDPORT_AHB_MPU_TABLE_0_REG AddressType = 0x3FF000B4 AdrBeginDPORT_AHB_MPU_TABLE_1_REG AddressType = 0x3FF000B8 AdrBeginDPORT_AHBLITE_MPU_TABLE_UART_REG AddressType = 0x3FF0032C AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI1_REG AddressType = 0x3FF00330 AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI0_REG AddressType = 0x3FF00334 AdrBeginDPORT_AHBLITE_MPU_TABLE_GPIO_REG AddressType = 0x3FF00338 AdrBeginDPORT_AHBLITE_MPU_TABLE_RTC_REG AddressType = 0x3FF00348 AdrBeginDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG AddressType = 0x3FF0034C AdrBeginDPORT_AHBLITE_MPU_TABLE_HINF_REG AddressType = 0x3FF00354 AdrBeginDPORT_AHBLITE_MPU_TABLE_UHCI1_REG AddressType = 0x3FF00358 AdrBeginDPORT_AHBLITE_MPU_TABLE_I2S0_REG AddressType = 0x3FF00364 AdrBeginDPORT_AHBLITE_MPU_TABLE_UART1_REG AddressType = 0x3FF00368 AdrBeginDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG AddressType = 0x3FF00374 AdrBeginDPORT_AHBLITE_MPU_TABLE_UHCI0_REG AddressType = 0x3FF00378 AdrBeginDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG AddressType = 0x3FF0037C AdrBeginDPORT_AHBLITE_MPU_TABLE_RMT_REG AddressType = 0x3FF00380 AdrBeginDPORT_AHBLITE_MPU_TABLE_PCNT_REG AddressType = 0x3FF00384 AdrBeginDPORT_AHBLITE_MPU_TABLE_SLC_REG AddressType = 0x3FF00388 AdrBeginDPORT_AHBLITE_MPU_TABLE_LEDC_REG AddressType = 0x3FF0038C AdrBeginDPORT_AHBLITE_MPU_TABLE_EFUSE_REG AddressType = 0x3FF00390 AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG AddressType = 0x3FF00394 AdrBeginDPORT_AHBLITE_MPU_TABLE_PWM0_REG AddressType = 0x3FF0039C AdrBeginDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG AddressType = 0x3FF003A0 AdrBeginDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG AddressType = 0x3FF003A4 AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI2_REG AddressType = 0x3FF003A8 AdrBeginDPORT_AHBLITE_MPU_TABLE_SPI3_REG AddressType = 0x3FF003AC AdrBeginDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG AddressType = 0x3FF003B0 AdrBeginDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG AddressType = 0x3FF003B4 AdrBeginDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG AddressType = 0x3FF003B8 AdrBeginDPORT_AHBLITE_MPU_TABLE_EMAC_REG AddressType = 0x3FF003BC AdrBeginDPORT_AHBLITE_MPU_TABLE_PWM1_REG AddressType = 0x3FF003C4 AdrBeginDPORT_AHBLITE_MPU_TABLE_I2S1_REG AddressType = 0x3FF003C8 AdrBeginDPORT_AHBLITE_MPU_TABLE_UART2_REG AddressType = 0x3FF003CC AdrBeginDPORT_AHBLITE_MPU_TABLE_PWR_REG AddressType = 0x3FF003E4 AdrBeginDPORT_IMMU_TABLE0_REG AddressType = 0x3FF00504 AdrBeginDPORT_IMMU_TABLE1_REG AddressType = 0x3FF00508 AdrBeginDPORT_IMMU_TABLE2_REG AddressType = 0x3FF0050C AdrBeginDPORT_IMMU_TABLE3_REG AddressType = 0x3FF00510 AdrBeginDPORT_IMMU_TABLE4_REG AddressType = 0x3FF00514 AdrBeginDPORT_IMMU_TABLE5_REG AddressType = 0x3FF00518 AdrBeginDPORT_IMMU_TABLE6_REG AddressType = 0x3FF0051C AdrBeginDPORT_IMMU_TABLE7_REG AddressType = 0x3FF00520 AdrBeginDPORT_IMMU_TABLE8_REG AddressType = 0x3FF00524 AdrBeginDPORT_IMMU_TABLE9_REG AddressType = 0x3FF00528 AdrBeginDPORT_IMMU_TABLE10_REG AddressType = 0x3FF0052C AdrBeginDPORT_IMMU_TABLE11_REG AddressType = 0x3FF00530 AdrBeginDPORT_IMMU_TABLE12_REG AddressType = 0x3FF00534 AdrBeginDPORT_IMMU_TABLE13_REG AddressType = 0x3FF00538 AdrBeginDPORT_IMMU_TABLE14_REG AddressType = 0x3FF0053C AdrBeginDPORT_IMMU_TABLE15_REG AddressType = 0x3FF00540 AdrBeginDPORT_DMMU_TABLE0_REG AddressType = 0x3FF00544 AdrBeginDPORT_DMMU_TABLE1_REG AddressType = 0x3FF00548 AdrBeginDPORT_DMMU_TABLE2_REG AddressType = 0x3FF0054C AdrBeginDPORT_DMMU_TABLE3_REG AddressType = 0x3FF00550 AdrBeginDPORT_DMMU_TABLE4_REG AddressType = 0x3FF00554 AdrBeginDPORT_DMMU_TABLE5_REG AddressType = 0x3FF00558 AdrBeginDPORT_DMMU_TABLE6_REG AddressType = 0x3FF0055C AdrBeginDPORT_DMMU_TABLE7_REG AddressType = 0x3FF00560 AdrBeginDPORT_DMMU_TABLE8_REG AddressType = 0x3FF00564 AdrBeginDPORT_DMMU_TABLE9_REG AddressType = 0x3FF00568 AdrBeginDPORT_DMMU_TABLE10_REG AddressType = 0x3FF0056C AdrBeginDPORT_DMMU_TABLE11_REG AddressType = 0x3FF00570 AdrBeginDPORT_DMMU_TABLE12_REG AddressType = 0x3FF00574 AdrBeginDPORT_DMMU_TABLE13_REG AddressType = 0x3FF00578 AdrBeginDPORT_DMMU_TABLE14_REG AddressType = 0x3FF0057C AdrBeginDPORT_DMMU_TABLE15_REG AddressType = 0x3FF00580 AdrBeginDPORT_APPCPU_CTRL_REG_A_REG AddressType = 0x3FF0002C AdrBeginDPORT_APPCPU_CTRL_REG_B_REG AddressType = 0x3FF00030 AdrBeginDPORT_APPCPU_CTRL_REG_C_REG AddressType = 0x3FF00034 AdrBeginDPORT_APPCPU_CTRL_REG_D_REG AddressType = 0x3FF00038 AdrBeginDPORT_PERI_CLK_EN_REG AddressType = 0x3FF0001C AdrBeginDPORT_PERI_RST_EN_REG AddressType = 0x3FF00020 AdrBeginDPORT_PERIP_CLK_EN_REG AddressType = 0x3FF000C0 AdrBeginDPORT_PERIP_RST_EN_REG AddressType = 0x3FF000C4 AdrBeginDPORT_WIFI_CLK_EN_REG AddressType = 0x3FF000CC AdrBeginDPORT_WIFI_RST_EN_REG AddressType = 0x3FF000D0 )
const ( AdrEndDPORT_PRO_BOOT_REMAP_CTRL_REG AddressType = 0x3FF00004 AdrEndDPORT_APP_BOOT_REMAP_CTRL_REG AddressType = 0x3FF0007C AdrEndDPORT_CACHE_MUX_MODE_REG AddressType = 0x3FF0003C AdrEndDPORT_CPU_PER_CONF_REG AddressType = 0x3FF000DC AdrEndDPORT_CPU_INTR_FROM_CPU_0_REG AddressType = 0x3FF000E0 AdrEndDPORT_CPU_INTR_FROM_CPU_1_REG AddressType = 0x3FF000E4 AdrEndDPORT_CPU_INTR_FROM_CPU_2_REG AddressType = 0x3FF000E8 AdrEndDPORT_CPU_INTR_FROM_CPU_3_REG AddressType = 0x3FF000EC AdrEndDPORT_PRO_INTR_STATUS_REG_0_REG AddressType = 0x3FF000F0 AdrEndDPORT_PRO_INTR_STATUS_REG_1_REG AddressType = 0x3FF000F4 AdrEndDPORT_PRO_INTR_STATUS_REG_2_REG AddressType = 0x3FF000F8 AdrEndDPORT_APP_INTR_STATUS_REG_0_REG AddressType = 0x3FF000FC AdrEndDPORT_APP_INTR_STATUS_REG_1_REG AddressType = 0x3FF00100 AdrEndDPORT_APP_INTR_STATUS_REG_2_REG AddressType = 0x3FF00104 AdrEndDPORT_PRO_MAC_INTR_MAP_REG AddressType = 0x3FF00108 AdrEndDPORT_PRO_MAC_NMI_MAP_REG AddressType = 0x3FF0010C AdrEndDPORT_PRO_BB_INT_MAP_REG AddressType = 0x3FF00110 AdrEndDPORT_PRO_BT_MAC_INT_MAP_REG AddressType = 0x3FF00114 AdrEndDPORT_PRO_BT_BB_INT_MAP_REG AddressType = 0x3FF00118 AdrEndDPORT_PRO_BT_BB_NMI_MAP_REG AddressType = 0x3FF0011C AdrEndDPORT_PRO_RWBT_IRQ_MAP_REG AddressType = 0x3FF00120 AdrEndDPORT_PRO_RWBLE_IRQ_MAP_REG AddressType = 0x3FF00124 AdrEndDPORT_PRO_RWBT_NMI_MAP_REG AddressType = 0x3FF00128 AdrEndDPORT_PRO_RWBLE_NMI_MAP_REG AddressType = 0x3FF0012C AdrEndDPORT_PRO_SLC0_INTR_MAP_REG AddressType = 0x3FF00130 AdrEndDPORT_PRO_SLC1_INTR_MAP_REG AddressType = 0x3FF00134 AdrEndDPORT_PRO_UHCI0_INTR_MAP_REG AddressType = 0x3FF00138 AdrEndDPORT_PRO_UHCI1_INTR_MAP_REG AddressType = 0x3FF0013C AdrEndDPORT_PRO_TG_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF00140 AdrEndDPORT_PRO_TG_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00144 AdrEndDPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF00148 AdrEndDPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF0014C AdrEndDPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF00150 AdrEndDPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00154 AdrEndDPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF00158 AdrEndDPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF0015C AdrEndDPORT_PRO_GPIO_INTERRUPT_MAP_REG AddressType = 0x3FF00160 AdrEndDPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG AddressType = 0x3FF00164 AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG AddressType = 0x3FF00168 AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG AddressType = 0x3FF0016C AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG AddressType = 0x3FF00170 AdrEndDPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG AddressType = 0x3FF00174 AdrEndDPORT_PRO_SPI_INTR_0_MAP_REG AddressType = 0x3FF00178 AdrEndDPORT_PRO_SPI_INTR_1_MAP_REG AddressType = 0x3FF0017C AdrEndDPORT_PRO_SPI_INTR_2_MAP_REG AddressType = 0x3FF00180 AdrEndDPORT_PRO_SPI_INTR_3_MAP_REG AddressType = 0x3FF00184 AdrEndDPORT_PRO_I2S0_INT_MAP_REG AddressType = 0x3FF00188 AdrEndDPORT_PRO_I2S1_INT_MAP_REG AddressType = 0x3FF0018C AdrEndDPORT_PRO_UART_INTR_MAP_REG AddressType = 0x3FF00190 AdrEndDPORT_PRO_UART1_INTR_MAP_REG AddressType = 0x3FF00194 AdrEndDPORT_PRO_UART2_INTR_MAP_REG AddressType = 0x3FF00198 AdrEndDPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG AddressType = 0x3FF0019C AdrEndDPORT_PRO_EMAC_INT_MAP_REG AddressType = 0x3FF001A0 AdrEndDPORT_PRO_PWM0_INTR_MAP_REG AddressType = 0x3FF001A4 AdrEndDPORT_PRO_PWM1_INTR_MAP_REG AddressType = 0x3FF001B0 AdrEndDPORT_PRO_LEDC_INT_MAP_REG AddressType = 0x3FF001B4 AdrEndDPORT_PRO_EFUSE_INT_MAP_REG AddressType = 0x3FF001B8 AdrEndDPORT_PRO_TWAI_INT_MAP_REG AddressType = 0x3FF001BC AdrEndDPORT_PRO_RTC_CORE_INTR_MAP_REG AddressType = 0x3FF001C0 AdrEndDPORT_PRO_RMT_INTR_MAP_REG AddressType = 0x3FF001C4 AdrEndDPORT_PRO_PCNT_INTR_MAP_REG AddressType = 0x3FF001C8 AdrEndDPORT_PRO_I2C_EXT0_INTR_MAP_REG AddressType = 0x3FF001CC AdrEndDPORT_PRO_I2C_EXT1_INTR_MAP_REG AddressType = 0x3FF001D0 AdrEndDPORT_PRO_RSA_INTR_MAP_REG AddressType = 0x3FF001D4 AdrEndDPORT_PRO_SPI1_DMA_INT_MAP_REG AddressType = 0x3FF001D8 AdrEndDPORT_PRO_SPI2_DMA_INT_MAP_REG AddressType = 0x3FF001DC AdrEndDPORT_PRO_SPI3_DMA_INT_MAP_REG AddressType = 0x3FF001E0 AdrEndDPORT_PRO_WDG_INT_MAP_REG AddressType = 0x3FF001E4 AdrEndDPORT_PRO_TIMER_INT1_MAP_REG AddressType = 0x3FF001E8 AdrEndDPORT_PRO_TIMER_INT2_MAP_REG AddressType = 0x3FF001EC AdrEndDPORT_PRO_TG_T0_EDGE_INT_MAP_REG AddressType = 0x3FF001F0 AdrEndDPORT_PRO_TG_T1_EDGE_INT_MAP_REG AddressType = 0x3FF001F4 AdrEndDPORT_PRO_TG_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF001F8 AdrEndDPORT_PRO_TG_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF001FC AdrEndDPORT_PRO_TG1_T0_EDGE_INT_MAP_REG AddressType = 0x3FF00200 AdrEndDPORT_PRO_TG1_T1_EDGE_INT_MAP_REG AddressType = 0x3FF00204 AdrEndDPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF00208 AdrEndDPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF0020C AdrEndDPORT_PRO_MMU_IA_INT_MAP_REG AddressType = 0x3FF00210 AdrEndDPORT_PRO_MPU_IA_INT_MAP_REG AddressType = 0x3FF00214 AdrEndDPORT_PRO_CACHE_IA_INT_MAP_REG AddressType = 0x3FF00218 AdrEndDPORT_APP_MAC_INTR_MAP_REG AddressType = 0x3FF0021C AdrEndDPORT_APP_MAC_NMI_MAP_REG AddressType = 0x3FF00220 AdrEndDPORT_APP_BB_INT_MAP_REG AddressType = 0x3FF00224 AdrEndDPORT_APP_BT_MAC_INT_MAP_REG AddressType = 0x3FF00228 AdrEndDPORT_APP_BT_BB_INT_MAP_REG AddressType = 0x3FF0022C AdrEndDPORT_APP_BT_BB_NMI_MAP_REG AddressType = 0x3FF00230 AdrEndDPORT_APP_RWBT_IRQ_MAP_REG AddressType = 0x3FF00234 AdrEndDPORT_APP_RWBLE_IRQ_MAP_REG AddressType = 0x3FF00238 AdrEndDPORT_APP_RWBT_NMI_MAP_REG AddressType = 0x3FF0023C AdrEndDPORT_APP_RWBLE_NMI_MAP_REG AddressType = 0x3FF00240 AdrEndDPORT_APP_SLC0_INTR_MAP_REG AddressType = 0x3FF00244 AdrEndDPORT_APP_SLC1_INTR_MAP_REG AddressType = 0x3FF00248 AdrEndDPORT_APP_UHCI0_INTR_MAP_REG AddressType = 0x3FF0024C AdrEndDPORT_APP_UHCI1_INTR_MAP_REG AddressType = 0x3FF00250 AdrEndDPORT_APP_TG_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF00254 AdrEndDPORT_APP_TG_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00258 AdrEndDPORT_APP_TG_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF0025C AdrEndDPORT_APP_TG_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF00260 AdrEndDPORT_APP_TG1_T0_LEVEL_INT_MAP_REG AddressType = 0x3FF00264 AdrEndDPORT_APP_TG1_T1_LEVEL_INT_MAP_REG AddressType = 0x3FF00268 AdrEndDPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG AddressType = 0x3FF0026C AdrEndDPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG AddressType = 0x3FF00270 AdrEndDPORT_APP_GPIO_INTERRUPT_MAP_REG AddressType = 0x3FF00274 AdrEndDPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG AddressType = 0x3FF00278 AdrEndDPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG AddressType = 0x3FF0027C AdrEndDPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG AddressType = 0x3FF00280 AdrEndDPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG AddressType = 0x3FF00284 AdrEndDPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG AddressType = 0x3FF00288 AdrEndDPORT_APP_SPI_INTR_0_MAP_REG AddressType = 0x3FF0028C AdrEndDPORT_APP_SPI_INTR_1_MAP_REG AddressType = 0x3FF00290 AdrEndDPORT_APP_SPI_INTR_2_MAP_REG AddressType = 0x3FF00294 AdrEndDPORT_APP_SPI_INTR_3_MAP_REG AddressType = 0x3FF00298 AdrEndDPORT_APP_I2S0_INT_MAP_REG AddressType = 0x3FF0029C AdrEndDPORT_APP_I2S1_INT_MAP_REG AddressType = 0x3FF002A0 AdrEndDPORT_APP_UART_INTR_MAP_REG AddressType = 0x3FF002A4 AdrEndDPORT_APP_UART1_INTR_MAP_REG AddressType = 0x3FF002A8 AdrEndDPORT_APP_UART2_INTR_MAP_REG AddressType = 0x3FF002AC AdrEndDPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG AddressType = 0x3FF002B0 AdrEndDPORT_APP_EMAC_INT_MAP_REG AddressType = 0x3FF002B4 AdrEndDPORT_APP_PWM0_INTR_MAP_REG AddressType = 0x3FF002B8 AdrEndDPORT_APP_PWM1_INTR_MAP_REG AddressType = 0x3FF002C4 AdrEndDPORT_APP_LEDC_INT_MAP_REG AddressType = 0x3FF002C8 AdrEndDPORT_APP_EFUSE_INT_MAP_REG AddressType = 0x3FF002CC AdrEndDPORT_APP_TWAI_INT_MAP_REG AddressType = 0x3FF002D0 AdrEndDPORT_APP_RTC_CORE_INTR_MAP_REG AddressType = 0x3FF002D4 AdrEndDPORT_APP_RMT_INTR_MAP_REG AddressType = 0x3FF002D8 AdrEndDPORT_APP_PCNT_INTR_MAP_REG AddressType = 0x3FF002DC AdrEndDPORT_APP_I2C_EXT0_INTR_MAP_REG AddressType = 0x3FF002E0 AdrEndDPORT_APP_I2C_EXT1_INTR_MAP_REG AddressType = 0x3FF002E4 AdrEndDPORT_APP_RSA_INTR_MAP_REG AddressType = 0x3FF002E8 AdrEndDPORT_APP_SPI1_DMA_INT_MAP_REG AddressType = 0x3FF002EC AdrEndDPORT_APP_SPI2_DMA_INT_MAP_REG AddressType = 0x3FF002F0 AdrEndDPORT_APP_SPI3_DMA_INT_MAP_REG AddressType = 0x3FF002F4 AdrEndDPORT_APP_WDG_INT_MAP_REG AddressType = 0x3FF002F8 AdrEndDPORT_APP_TIMER_INT1_MAP_REG AddressType = 0x3FF002FC AdrEndDPORT_APP_TIMER_INT2_MAP_REG AddressType = 0x3FF00300 AdrEndDPORT_APP_TG_T0_EDGE_INT_MAP_REG AddressType = 0x3FF00304 AdrEndDPORT_APP_TG_T1_EDGE_INT_MAP_REG AddressType = 0x3FF00308 AdrEndDPORT_APP_TG_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF0030C AdrEndDPORT_APP_TG_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF00310 AdrEndDPORT_APP_TG1_T0_EDGE_INT_MAP_REG AddressType = 0x3FF00314 AdrEndDPORT_APP_TG1_T1_EDGE_INT_MAP_REG AddressType = 0x3FF00318 AdrEndDPORT_APP_TG1_WDT_EDGE_INT_MAP_REG AddressType = 0x3FF0031C AdrEndDPORT_APP_TG1_LACT_EDGE_INT_MAP_REG AddressType = 0x3FF00320 AdrEndDPORT_APP_MMU_IA_INT_MAP_REG AddressType = 0x3FF00324 AdrEndDPORT_APP_MPU_IA_INT_MAP_REG AddressType = 0x3FF00328 AdrEndDPORT_APP_CACHE_IA_INT_MAP_REG AddressType = 0x3FF005A8 AdrEndDPORT_SPI_DMA_CHAN_SEL_REG AddressType = 0x3FF00040 AdrEndDPORT_PRO_CACHE_CTRL_REG AddressType = 0x3FF00044 AdrEndDPORT_PRO_CACHE_CTRL1_REG AddressType = 0x3FF00058 AdrEndDPORT_APP_CACHE_CTRL_REG AddressType = 0x3FF0005C AdrEndDPORT_APP_CACHE_CTRL1_REG AddressType = 0x3FF00080 AdrEndDPORT_IMMU_PAGE_MODE_REG AddressType = 0x3FF00084 AdrEndDPORT_DMMU_PAGE_MODE_REG AddressType = 0x3FF000B4 AdrEndDPORT_AHB_MPU_TABLE_0_REG AddressType = 0x3FF000B8 AdrEndDPORT_AHB_MPU_TABLE_1_REG AddressType = 0x3FF0032C AdrEndDPORT_AHBLITE_MPU_TABLE_UART_REG AddressType = 0x3FF00330 AdrEndDPORT_AHBLITE_MPU_TABLE_SPI1_REG AddressType = 0x3FF00334 AdrEndDPORT_AHBLITE_MPU_TABLE_SPI0_REG AddressType = 0x3FF00338 AdrEndDPORT_AHBLITE_MPU_TABLE_GPIO_REG AddressType = 0x3FF00348 AdrEndDPORT_AHBLITE_MPU_TABLE_RTC_REG AddressType = 0x3FF0034C AdrEndDPORT_AHBLITE_MPU_TABLE_IO_MUX_REG AddressType = 0x3FF00354 AdrEndDPORT_AHBLITE_MPU_TABLE_HINF_REG AddressType = 0x3FF00358 AdrEndDPORT_AHBLITE_MPU_TABLE_UHCI1_REG AddressType = 0x3FF00364 AdrEndDPORT_AHBLITE_MPU_TABLE_I2S0_REG AddressType = 0x3FF00368 AdrEndDPORT_AHBLITE_MPU_TABLE_UART1_REG AddressType = 0x3FF00374 AdrEndDPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG AddressType = 0x3FF00378 AdrEndDPORT_AHBLITE_MPU_TABLE_UHCI0_REG AddressType = 0x3FF0037C AdrEndDPORT_AHBLITE_MPU_TABLE_SLCHOST_REG AddressType = 0x3FF00380 AdrEndDPORT_AHBLITE_MPU_TABLE_RMT_REG AddressType = 0x3FF00384 AdrEndDPORT_AHBLITE_MPU_TABLE_PCNT_REG AddressType = 0x3FF00388 AdrEndDPORT_AHBLITE_MPU_TABLE_SLC_REG AddressType = 0x3FF0038C AdrEndDPORT_AHBLITE_MPU_TABLE_LEDC_REG AddressType = 0x3FF00390 AdrEndDPORT_AHBLITE_MPU_TABLE_EFUSE_REG AddressType = 0x3FF00394 AdrEndDPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG AddressType = 0x3FF0039C AdrEndDPORT_AHBLITE_MPU_TABLE_PWM0_REG AddressType = 0x3FF003A0 AdrEndDPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG AddressType = 0x3FF003A4 AdrEndDPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG AddressType = 0x3FF003A8 AdrEndDPORT_AHBLITE_MPU_TABLE_SPI2_REG AddressType = 0x3FF003AC AdrEndDPORT_AHBLITE_MPU_TABLE_SPI3_REG AddressType = 0x3FF003B0 AdrEndDPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG AddressType = 0x3FF003B4 AdrEndDPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG AddressType = 0x3FF003B8 AdrEndDPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG AddressType = 0x3FF003BC AdrEndDPORT_AHBLITE_MPU_TABLE_EMAC_REG AddressType = 0x3FF003C4 AdrEndDPORT_AHBLITE_MPU_TABLE_PWM1_REG AddressType = 0x3FF003C8 AdrEndDPORT_AHBLITE_MPU_TABLE_I2S1_REG AddressType = 0x3FF003CC AdrEndDPORT_AHBLITE_MPU_TABLE_UART2_REG AddressType = 0x3FF003E4 AdrEndDPORT_AHBLITE_MPU_TABLE_PWR_REG AddressType = 0x3FF00504 AdrEndDPORT_IMMU_TABLE0_REG AddressType = 0x3FF00508 AdrEndDPORT_IMMU_TABLE1_REG AddressType = 0x3FF0050C AdrEndDPORT_IMMU_TABLE2_REG AddressType = 0x3FF00510 AdrEndDPORT_IMMU_TABLE3_REG AddressType = 0x3FF00514 AdrEndDPORT_IMMU_TABLE4_REG AddressType = 0x3FF00518 AdrEndDPORT_IMMU_TABLE5_REG AddressType = 0x3FF0051C AdrEndDPORT_IMMU_TABLE6_REG AddressType = 0x3FF00520 AdrEndDPORT_IMMU_TABLE7_REG AddressType = 0x3FF00524 AdrEndDPORT_IMMU_TABLE8_REG AddressType = 0x3FF00528 AdrEndDPORT_IMMU_TABLE9_REG AddressType = 0x3FF0052C AdrEndDPORT_IMMU_TABLE10_REG AddressType = 0x3FF00530 AdrEndDPORT_IMMU_TABLE11_REG AddressType = 0x3FF00534 AdrEndDPORT_IMMU_TABLE12_REG AddressType = 0x3FF00538 AdrEndDPORT_IMMU_TABLE13_REG AddressType = 0x3FF0053C AdrEndDPORT_IMMU_TABLE14_REG AddressType = 0x3FF00540 AdrEndDPORT_IMMU_TABLE15_REG AddressType = 0x3FF00544 AdrEndDPORT_DMMU_TABLE0_REG AddressType = 0x3FF00548 AdrEndDPORT_DMMU_TABLE1_REG AddressType = 0x3FF0054C AdrEndDPORT_DMMU_TABLE2_REG AddressType = 0x3FF00550 AdrEndDPORT_DMMU_TABLE3_REG AddressType = 0x3FF00554 AdrEndDPORT_DMMU_TABLE4_REG AddressType = 0x3FF00558 AdrEndDPORT_DMMU_TABLE5_REG AddressType = 0x3FF0055C AdrEndDPORT_DMMU_TABLE6_REG AddressType = 0x3FF00560 AdrEndDPORT_DMMU_TABLE7_REG AddressType = 0x3FF00564 AdrEndDPORT_DMMU_TABLE8_REG AddressType = 0x3FF00568 AdrEndDPORT_DMMU_TABLE9_REG AddressType = 0x3FF0056C AdrEndDPORT_DMMU_TABLE10_REG AddressType = 0x3FF00570 AdrEndDPORT_DMMU_TABLE11_REG AddressType = 0x3FF00574 AdrEndDPORT_DMMU_TABLE12_REG AddressType = 0x3FF00578 AdrEndDPORT_DMMU_TABLE13_REG AddressType = 0x3FF0057C AdrEndDPORT_DMMU_TABLE14_REG AddressType = 0x3FF00580 AdrEndDPORT_DMMU_TABLE15_REG AddressType = 0x3FF0002C AdrEndDPORT_APPCPU_CTRL_REG_A_REG AddressType = 0x3FF00030 AdrEndDPORT_APPCPU_CTRL_REG_B_REG AddressType = 0x3FF00034 AdrEndDPORT_APPCPU_CTRL_REG_C_REG AddressType = 0x3FF00038 AdrEndDPORT_APPCPU_CTRL_REG_D_REG AddressType = 0x3FF0001C AdrEndDPORT_PERI_CLK_EN_REG AddressType = 0x3FF00020 AdrEndDPORT_PERI_RST_EN_REG AddressType = 0x3FF000C0 AdrEndDPORT_PERIP_CLK_EN_REG AddressType = 0x3FF000C4 AdrEndDPORT_PERIP_RST_EN_REG AddressType = 0x3FF000CC AdrEndDPORT_WIFI_CLK_EN_REG AddressType = 0x3FF000D0 AdrEndDPORT_WIFI_RST_EN_REG AddressType = 0x3FF000D0 + 32 )
const ( AdrBeginSYSCON_SYSCLK_CONF_REG AddressType = 0x0000 AdrBeginSYSCON_XTAL_TICK_CONF_REG AddressType = 0x0004 AdrBeginSYSCON_PLL_TICK_CONF_REG AddressType = 0x0008 AdrBeginSYSCON_CK8M_TICK_CONF_REG AddressType = 0x000C AdrBeginSYSCON_APLL_TICK_CONF_REG AddressType = 0x003C AdrBeginSYSCON_DATE_REG AddressType = 0x007C )
const ( AdrEndSYSCON_SYSCLK_CONF_REG AddressType = 0x0004 AdrEndSYSCON_XTAL_TICK_CONF_REG AddressType = 0x0008 AdrEndSYSCON_PLL_TICK_CONF_REG AddressType = 0x000C AdrEndSYSCON_CK8M_TICK_CONF_REG AddressType = 0x003C AdrEndSYSCON_APLL_TICK_CONF_REG AddressType = 0x007C AdrEndSYSCON_DATE_REG AddressType = 0x007C + 5 )
const ( AdrBeginDPortRegister AddressType = 0x3FF0_0000 AdrBeginAESAccelerator AddressType = 0x3FF0_1000 AdrBeginRSAAccelerator AddressType = 0x3FF0_2000 AdrBeginSHAAccelerator AddressType = 0x3FF0_3000 AdrBeginSecureBoot AddressType = 0x3FF0_4000 AdrBeginCacheMMUTable AddressType = 0x3FF1_0000 AdrBeginPIDController AddressType = 0x3FF1_F000 AdrBeginUART0 AddressType = 0x3FF4_0000 AdrBeginSPI1 AddressType = 0x3FF4_2000 AdrBeginSPI0 AddressType = 0x3FF4_3000 AdrBeginGPIO AddressType = 0x3FF4_4000 AdrBeginRTC AddressType = 0x3FF4_8000 AdrBeginIOMUX AddressType = 0x3FF4_9000 AdrBeginSDIOSlave1 AddressType = 0x3FF4_B000 AdrBeginUDMA1 AddressType = 0x3FF4_C000 AdrBeginI2S0 AddressType = 0x3FF4_F000 AdrBeginUART1 AddressType = 0x3FF5_0000 AdrBeginI2C0 AddressType = 0x3FF5_3000 AdrBeginUDMA0 AddressType = 0x3FF5_4000 AdrBeginSDIOSlave2 AddressType = 0x3FF5_5000 AdrBeginRMT AddressType = 0x3FF5_6000 AdrBeginPCNT AddressType = 0x3FF5_7000 AdrBeginSDIOSlave3 AddressType = 0x3FF5_8000 AdrBeginLEDPWM AddressType = 0x3FF5_9000 AdrBeginEFuseController AddressType = 0x3FF5_A000 AdrBeginFlashEncryption AddressType = 0x3FF5_B000 AdrBeginMCPWM0 AddressType = 0x3FF5_E000 AdrBeginTIMG0 AddressType = 0x3FF5_F000 AdrBeginTIMG1 AddressType = 0x3FF6_0000 AdrBeginSPI2 AddressType = 0x3FF6_4000 AdrBeginSPI3 AddressType = 0x3FF6_5000 AdrBeginSYSCON AddressType = 0x3FF6_6000 AdrBeginI2C1 AddressType = 0x3FF6_7000 AdrBeginSDMMC AddressType = 0x3FF6_8000 AdrBeginEMAC AddressType = 0x3FF6_9000 AdrBeginTWAI AddressType = 0x3FF6_B000 AdrBeginMCPWM1 AddressType = 0x3FF6_C000 AdrBeginI2S1 AddressType = 0x3FF6_D000 AdrBeginUART2 AddressType = 0x3FF6_E000 AdrBeginRNG AddressType = 0x3FF7_5000 )
const ( AdrEndDPortRegister AddressType = 0x3FF0_0FFF AdrEndAESAccelerator AddressType = 0x3FF0_1FFF AdrEndRSAAccelerator AddressType = 0x3FF0_2FFF AdrEndSHAAccelerator AddressType = 0x3FF0_3FFF AdrEndSecureBoot AddressType = 0x3FF0_4FFF AdrEndCacheMMUTable AddressType = 0x3FF1_3FFF AdrEndPIDController AddressType = 0x3FF1_FFFF AdrEndUART0 AddressType = 0x3FF4_0FFF AdrEndSPI1 AddressType = 0x3FF4_2FFF AdrEndSPI0 AddressType = 0x3FF4_3FFF AdrEndGPIO AddressType = 0x3FF4_4FFF AdrEndRTC AddressType = 0x3FF4_8FFF AdrEndIOMUX AddressType = 0x3FF4_9FFF AdrEndSDIOSlave1 AddressType = 0x3FF4_BFFF AdrEndUDMA1 AddressType = 0x3FF4_CFFF AdrEndI2S0 AddressType = 0x3FF4_FFFF AdrEndUART1 AddressType = 0x3FF5_0FFF AdrEndI2C0 AddressType = 0x3FF5_3FFF AdrEndUDMA0 AddressType = 0x3FF5_4FFF AdrEndSDIOSlave2 AddressType = 0x3FF5_5FFF AdrEndRMT AddressType = 0x3FF5_6FFF AdrEndPCNT AddressType = 0x3FF5_7FFF AdrEndSDIOSlave3 AddressType = 0x3FF5_8FFF AdrEndLEDPWM AddressType = 0x3FF5_9FFF AdrEndEFuseController AddressType = 0x3FF5_AFFF AdrEndFlashEncryption AddressType = 0x3FF5_BFFF AdrEndMCPWM0 AddressType = 0x3FF5_EFFF AdrEndTIMG0 AddressType = 0x3FF5_FFFF AdrEndTIMG1 AddressType = 0x3FF6_0FFF AdrEndSPI2 AddressType = 0x3FF6_4FFF AdrEndSPI3 AddressType = 0x3FF6_5FFF AdrEndSYSCON AddressType = 0x3FF6_6FFF AdrEndI2C1 AddressType = 0x3FF6_7FFF AdrEndSDMMC AddressType = 0x3FF6_8FFF AdrEndEMAC AddressType = 0x3FF6_AFFF AdrEndTWAI AddressType = 0x3FF6_BFFF AdrEndMCPWM1 AddressType = 0x3FF6_CFFF AdrEndI2S1 AddressType = 0x3FF6_DFFF AdrEndUART2 AddressType = 0x3FF6_EFFF AdrEndRNG AddressType = 0x3FF7_5FFF )
type DPortType ¶
type DPortType byte
const ( DPORT_PRO_BOOT_REMAP_CTRL_REG DPortType = 2 // R/W; remap mode for PRO_CPU DPORT_APP_BOOT_REMAP_CTRL_REG DPortType = 3 // R/W; remap mode for APP_CPU DPORT_CACHE_MUX_MODE_REG DPortType = 4 // R/W; the mode of the two caches sharing the memory DPORT_CPU_PER_CONF_REG DPortType = 5 // R/W; Selects CPU clock DPORT_CPU_INTR_FROM_CPU_0_REG DPortType = 6 // R/W; interrupt 0 in both CPUs DPORT_CPU_INTR_FROM_CPU_1_REG DPortType = 7 // R/W; interrupt 1 in both CPUs DPORT_CPU_INTR_FROM_CPU_2_REG DPortType = 8 // R/W; interrupt 2 in both CPUs DPORT_CPU_INTR_FROM_CPU_3_REG DPortType = 9 // R/W; interrupt 3 in both CPUs DPORT_PRO_INTR_STATUS_REG_0_REG DPortType = 10 // RO; PRO_CPU interrupt status 0 DPORT_PRO_INTR_STATUS_REG_1_REG DPortType = 11 // RO; PRO_CPU interrupt status 1 DPORT_PRO_INTR_STATUS_REG_2_REG DPortType = 12 // RO; PRO_CPU interrupt status 2 DPORT_APP_INTR_STATUS_REG_0_REG DPortType = 13 // RO; APP_CPU interrupt status 0 DPORT_APP_INTR_STATUS_REG_1_REG DPortType = 14 // RO; APP_CPU interrupt status 1 DPORT_APP_INTR_STATUS_REG_2_REG DPortType = 15 // RO; APP_CPU interrupt status 2 DPORT_PRO_MAC_INTR_MAP_REG DPortType = 16 // R/W; interrupt map DPORT_PRO_MAC_NMI_MAP_REG DPortType = 17 // R/W; interrupt map DPORT_PRO_BB_INT_MAP_REG DPortType = 18 // R/W; interrupt map DPORT_PRO_BT_MAC_INT_MAP_REG DPortType = 19 // R/W; interrupt map DPORT_PRO_BT_BB_INT_MAP_REG DPortType = 20 // R/W; interrupt map DPORT_PRO_BT_BB_NMI_MAP_REG DPortType = 21 // R/W; interrupt map DPORT_PRO_RWBT_IRQ_MAP_REG DPortType = 22 // R/W; interrupt map DPORT_PRO_RWBLE_IRQ_MAP_REG DPortType = 23 // R/W; interrupt map DPORT_PRO_RWBT_NMI_MAP_REG DPortType = 24 // R/W; interrupt map DPORT_PRO_RWBLE_NMI_MAP_REG DPortType = 25 // R/W; interrupt map DPORT_PRO_SLC0_INTR_MAP_REG DPortType = 26 // R/W; interrupt map DPORT_PRO_SLC1_INTR_MAP_REG DPortType = 27 // R/W; interrupt map DPORT_PRO_UHCI0_INTR_MAP_REG DPortType = 28 // R/W; interrupt map DPORT_PRO_UHCI1_INTR_MAP_REG DPortType = 29 // R/W; interrupt map DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG DPortType = 30 // R/W; interrupt map DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG DPortType = 31 // R/W; interrupt map DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG DPortType = 32 // R/W; interrupt map DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG DPortType = 33 // R/W; interrupt map DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG DPortType = 34 // R/W; interrupt map DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG DPortType = 35 // R/W; interrupt map DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG DPortType = 36 // R/W; interrupt map DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG DPortType = 37 // R/W; interrupt map DPORT_PRO_GPIO_INTERRUPT_MAP_REG DPortType = 38 // R/W; interrupt map DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG DPortType = 39 // R/W; interrupt map DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG DPortType = 40 // R/W; interrupt map DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG DPortType = 41 // R/W; interrupt map DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG DPortType = 42 // R/W; Interrupt map DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG DPortType = 43 // R/W; interrupt map DPORT_PRO_SPI_INTR_0_MAP_REG DPortType = 44 // R/W; interrupt map DPORT_PRO_SPI_INTR_1_MAP_REG DPortType = 45 // R/W; interrupt map DPORT_PRO_SPI_INTR_2_MAP_REG DPortType = 46 // R/W; interrupt map DPORT_PRO_SPI_INTR_3_MAP_REG DPortType = 47 // R/W; interrupt map DPORT_PRO_I2S0_INT_MAP_REG DPortType = 48 // R/W; interrupt map DPORT_PRO_I2S1_INT_MAP_REG DPortType = 49 // R/W; interrupt map DPORT_PRO_UART_INTR_MAP_REG DPortType = 50 // R/W; interrupt map DPORT_PRO_UART1_INTR_MAP_REG DPortType = 51 // R/W; interrupt map DPORT_PRO_UART2_INTR_MAP_REG DPortType = 52 // R/W; interrupt map DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG DPortType = 53 // R/W; interrupt map DPORT_PRO_EMAC_INT_MAP_REG DPortType = 54 // R/W; interrupt map DPORT_PRO_PWM0_INTR_MAP_REG DPortType = 55 // R/W; interrupt map DPORT_PRO_PWM1_INTR_MAP_REG DPortType = 56 // R/W; interrupt map DPORT_PRO_LEDC_INT_MAP_REG DPortType = 57 // R/W; interrupt map DPORT_PRO_EFUSE_INT_MAP_REG DPortType = 58 // R/W; interrupt map DPORT_PRO_TWAI_INT_MAP_REG DPortType = 59 // R/W; interrupt map DPORT_PRO_RTC_CORE_INTR_MAP_REG DPortType = 60 // R/W; interrupt map DPORT_PRO_RMT_INTR_MAP_REG DPortType = 61 // R/W; interrupt map DPORT_PRO_PCNT_INTR_MAP_REG DPortType = 62 // R/W; interrupt map DPORT_PRO_I2C_EXT0_INTR_MAP_REG DPortType = 63 // R/W; interrupt map DPORT_PRO_I2C_EXT1_INTR_MAP_REG DPortType = 64 // R/W; interrupt map DPORT_PRO_RSA_INTR_MAP_REG DPortType = 65 // R/W; interrupt map DPORT_PRO_SPI1_DMA_INT_MAP_REG DPortType = 66 // R/W; interrupt map DPORT_PRO_SPI2_DMA_INT_MAP_REG DPortType = 67 // R/W; interrupt map DPORT_PRO_SPI3_DMA_INT_MAP_REG DPortType = 68 // R/W; interrupt map DPORT_PRO_WDG_INT_MAP_REG DPortType = 69 // R/W; interrupt map DPORT_PRO_TIMER_INT1_MAP_REG DPortType = 70 // R/W; interrupt map DPORT_PRO_TIMER_INT2_MAP_REG DPortType = 71 // R/W; interrupt map DPORT_PRO_TG_T0_EDGE_INT_MAP_REG DPortType = 72 // R/W; interrupt map DPORT_PRO_TG_T1_EDGE_INT_MAP_REG DPortType = 73 // R/W; interrupt map DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG DPortType = 74 // R/W; interrupt map DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG DPortType = 75 // R/W; interrupt map DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG DPortType = 76 // R/W; interrupt map DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG DPortType = 77 // R/W; interrupt map DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG DPortType = 78 // R/W; interrupt map DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG DPortType = 79 // R/W; interrupt map DPORT_PRO_MMU_IA_INT_MAP_REG DPortType = 80 // R/W; interrupt map DPORT_PRO_MPU_IA_INT_MAP_REG DPortType = 81 // R/W; interrupt map DPORT_PRO_CACHE_IA_INT_MAP_REG DPortType = 82 // R/W; interrupt map DPORT_APP_MAC_INTR_MAP_REG DPortType = 83 // R/W; interrupt map DPORT_APP_MAC_NMI_MAP_REG DPortType = 84 // R/W; interrupt map DPORT_APP_BB_INT_MAP_REG DPortType = 85 // R/W; interrupt map DPORT_APP_BT_MAC_INT_MAP_REG DPortType = 86 // R/W; interrupt map DPORT_APP_BT_BB_INT_MAP_REG DPortType = 87 // R/W; interrupt map DPORT_APP_BT_BB_NMI_MAP_REG DPortType = 88 // R/W; interrupt map DPORT_APP_RWBT_IRQ_MAP_REG DPortType = 89 // R/W; interrupt map DPORT_APP_RWBLE_IRQ_MAP_REG DPortType = 90 // R/W; interrupt map DPORT_APP_RWBT_NMI_MAP_REG DPortType = 91 // R/W; interrupt map DPORT_APP_RWBLE_NMI_MAP_REG DPortType = 92 // R/W; interrupt map DPORT_APP_SLC0_INTR_MAP_REG DPortType = 93 // R/W; interrupt map DPORT_APP_SLC1_INTR_MAP_REG DPortType = 94 // R/W; interrupt map DPORT_APP_UHCI0_INTR_MAP_REG DPortType = 95 // R/W; interrupt map DPORT_APP_UHCI1_INTR_MAP_REG DPortType = 96 // R/W; interrupt map DPORT_APP_TG_T0_LEVEL_INT_MAP_REG DPortType = 97 // R/W; interrupt map DPORT_APP_TG_T1_LEVEL_INT_MAP_REG DPortType = 98 // R/W; interrupt map DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG DPortType = 99 // R/W; interrupt map DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG DPortType = 100 // R/W; interrupt map DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG DPortType = 101 // R/W; interrupt map DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG DPortType = 102 // R/W; interrupt map DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG DPortType = 103 // R/W; interrupt map DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG DPortType = 104 // R/W; interrupt map DPORT_APP_GPIO_INTERRUPT_MAP_REG DPortType = 105 // R/W; interrupt map DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG DPortType = 106 // R/W; interrupt map DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG DPortType = 107 // R/W; interrupt map DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG DPortType = 108 // R/W; interrupt map DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG DPortType = 109 // R/W; interrupt map DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG DPortType = 110 // R/W; interrupt map DPORT_APP_SPI_INTR_0_MAP_REG DPortType = 111 // R/W; interrupt map DPORT_APP_SPI_INTR_1_MAP_REG DPortType = 112 // R/W; interrupt map DPORT_APP_SPI_INTR_2_MAP_REG DPortType = 113 // R/W; interrupt map DPORT_APP_SPI_INTR_3_MAP_REG DPortType = 114 // R/W; interrupt map DPORT_APP_I2S0_INT_MAP_REG DPortType = 115 // R/W; interrupt map DPORT_APP_I2S1_INT_MAP_REG DPortType = 116 // R/W; interrupt map DPORT_APP_UART_INTR_MAP_REG DPortType = 117 // R/W; interrupt map DPORT_APP_UART1_INTR_MAP_REG DPortType = 118 // R/W; interrupt map DPORT_APP_UART2_INTR_MAP_REG DPortType = 119 // R/W; interrupt map DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG DPortType = 120 // R/W; interrupt map DPORT_APP_EMAC_INT_MAP_REG DPortType = 121 // R/W; interrupt map DPORT_APP_PWM0_INTR_MAP_REG DPortType = 122 // R/W; interrupt map DPORT_APP_PWM1_INTR_MAP_REG DPortType = 123 // R/W; interrupt map DPORT_APP_LEDC_INT_MAP_REG DPortType = 124 // R/W; interrupt map DPORT_APP_EFUSE_INT_MAP_REG DPortType = 125 // R/W; interrupt map DPORT_APP_TWAI_INT_MAP_REG DPortType = 126 // R/W; interrupt map DPORT_APP_RTC_CORE_INTR_MAP_REG DPortType = 127 // R/W; interrupt map DPORT_APP_RMT_INTR_MAP_REG DPortType = 128 // R/W; interrupt map DPORT_APP_PCNT_INTR_MAP_REG DPortType = 129 // R/W; interrupt map DPORT_APP_I2C_EXT0_INTR_MAP_REG DPortType = 130 // R/W; interrupt map DPORT_APP_I2C_EXT1_INTR_MAP_REG DPortType = 131 // R/W; interrupt map DPORT_APP_RSA_INTR_MAP_REG DPortType = 132 // R/W; interrupt map DPORT_APP_SPI1_DMA_INT_MAP_REG DPortType = 133 // R/W; interrupt map DPORT_APP_SPI2_DMA_INT_MAP_REG DPortType = 134 // R/W; interrupt map DPORT_APP_SPI3_DMA_INT_MAP_REG DPortType = 135 // R/W; interrupt map DPORT_APP_WDG_INT_MAP_REG DPortType = 136 // R/W; interrupt map DPORT_APP_TIMER_INT1_MAP_REG DPortType = 137 // R/W; interrupt map DPORT_APP_TIMER_INT2_MAP_REG DPortType = 138 // R/W; interrupt map DPORT_APP_TG_T0_EDGE_INT_MAP_REG DPortType = 139 // R/W; interrupt map DPORT_APP_TG_T1_EDGE_INT_MAP_REG DPortType = 140 // R/W; interrupt map DPORT_APP_TG_WDT_EDGE_INT_MAP_REG DPortType = 141 // R/W; interrupt map DPORT_APP_TG_LACT_EDGE_INT_MAP_REG DPortType = 142 // R/W; interrupt map DPORT_APP_TG1_T0_EDGE_INT_MAP_REG DPortType = 143 // R/W; interrupt map DPORT_APP_TG1_T1_EDGE_INT_MAP_REG DPortType = 144 // R/W; interrupt map DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG DPortType = 145 // R/W; interrupt map DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG DPortType = 146 // R/W; interrupt map DPORT_APP_MMU_IA_INT_MAP_REG DPortType = 147 // R/W; interrupt map DPORT_APP_MPU_IA_INT_MAP_REG DPortType = 148 // R/W; interrupt map DPORT_APP_CACHE_IA_INT_MAP_REG DPortType = 149 // R/W; interrupt map DPORT_SPI_DMA_CHAN_SEL_REG DPortType = 150 // R/W; selects DMA channel for SPI1 and SPI2 and SPI3 DPORT_PRO_CACHE_CTRL_REG DPortType = 151 // R/W; determines the virtual address mode of the external SRAM DPORT_PRO_CACHE_CTRL1_REG DPortType = 152 // R/W; PRO cache MMU configuration DPORT_APP_CACHE_CTRL_REG DPortType = 153 // R/W; determines the virtual address mode of the external SRAM DPORT_APP_CACHE_CTRL1_REG DPortType = 154 // R/W; APP cache MMU configuration DPORT_IMMU_PAGE_MODE_REG DPortType = 155 // R/W; page size in the MMU for the internal SRAM 0 DPORT_DMMU_PAGE_MODE_REG DPortType = 156 // R/W; page size in the MMU for the internal SRAM 2 DPORT_AHB_MPU_TABLE_0_REG DPortType = 157 // R/W; MPU for configuring DMA DPORT_AHB_MPU_TABLE_1_REG DPortType = 158 // R/W; MPU for configuring DMA DPORT_AHBLITE_MPU_TABLE_UART_REG DPortType = 159 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SPI1_REG DPortType = 160 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SPI0_REG DPortType = 161 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_GPIO_REG DPortType = 162 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_RTC_REG DPortType = 163 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG DPortType = 164 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_HINF_REG DPortType = 165 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_UHCI1_REG DPortType = 166 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_I2S0_REG DPortType = 167 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_UART1_REG DPortType = 168 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG DPortType = 169 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_UHCI0_REG DPortType = 170 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG DPortType = 171 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_RMT_REG DPortType = 172 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_PCNT_REG DPortType = 173 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SLC_REG DPortType = 174 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_LEDC_REG DPortType = 175 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_EFUSE_REG DPortType = 176 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG DPortType = 177 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_PWM0_REG DPortType = 178 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG DPortType = 179 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG DPortType = 180 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SPI2_REG DPortType = 181 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SPI3_REG DPortType = 182 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG DPortType = 183 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG DPortType = 184 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG DPortType = 185 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_EMAC_REG DPortType = 186 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_PWM1_REG DPortType = 187 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_I2S1_REG DPortType = 188 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_UART2_REG DPortType = 189 // R/W; MPU for peripherals DPORT_AHBLITE_MPU_TABLE_PWR_REG DPortType = 190 // R/W; MPU for peripherals DPORT_IMMU_TABLE0_REG DPortType = 191 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE1_REG DPortType = 192 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE2_REG DPortType = 193 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE3_REG DPortType = 194 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE4_REG DPortType = 195 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE5_REG DPortType = 196 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE6_REG DPortType = 197 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE7_REG DPortType = 198 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE8_REG DPortType = 199 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE9_REG DPortType = 200 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE10_REG DPortType = 201 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE11_REG DPortType = 202 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE12_REG DPortType = 203 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE13_REG DPortType = 204 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE14_REG DPortType = 205 // R/W; MMU register 1 for internal SRAM 0 DPORT_IMMU_TABLE15_REG DPortType = 206 // R/W; MMU register 1 for internal SRAM 0 DPORT_DMMU_TABLE0_REG DPortType = 207 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE1_REG DPortType = 208 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE2_REG DPortType = 209 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE3_REG DPortType = 210 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE4_REG DPortType = 211 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE5_REG DPortType = 212 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE6_REG DPortType = 213 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE7_REG DPortType = 214 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE8_REG DPortType = 215 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE9_REG DPortType = 216 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE10_REG DPortType = 217 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE11_REG DPortType = 218 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE12_REG DPortType = 219 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE13_REG DPortType = 220 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE14_REG DPortType = 221 // R/W; MMU register 1 for internal SRAM 2 DPORT_DMMU_TABLE15_REG DPortType = 222 // R/W; MMU register 1 for internal SRAM 2 DPORT_APPCPU_CTRL_REG_A_REG DPortType = 223 // R/W; reset for APP_CPU DPORT_APPCPU_CTRL_REG_B_REG DPortType = 224 // R/W; clock gate for APP_CPU DPORT_APPCPU_CTRL_REG_C_REG DPortType = 225 // R/W; stall for APP_CPU DPORT_APPCPU_CTRL_REG_D_REG DPortType = 226 // R/W; boot address for APP_CPU DPORT_PERI_CLK_EN_REG DPortType = 227 // R/W; clock gate for peripherals DPORT_PERI_RST_EN_REG DPortType = 228 // R/W; reset for peripherals DPORT_PERIP_CLK_EN_REG DPortType = 229 // R/W; clock gate for peripherals DPORT_PERIP_RST_EN_REG DPortType = 230 // R/W; reset for peripherals DPORT_WIFI_CLK_EN_REG DPortType = 231 // R/W; clock gate for Wi-Fi DPORT_WIFI_RST_EN_REG DPortType = 232 // R/W; reset for Wi-Fi )
type PeripheralType ¶
type PeripheralType byte
const ( DPortRegister PeripheralType = 2 //4 KB AESAccelerator PeripheralType = 3 //4 KB RSAAccelerator PeripheralType = 4 //4 KB SHAAccelerator PeripheralType = 5 //4 KB SecureBoot PeripheralType = 6 //4 KB CacheMMUTable PeripheralType = 7 //16 KB PIDController PeripheralType = 8 //4 KB Per-CPU peripheral UART0 PeripheralType = 9 //4 KB SPI1 PeripheralType = 10 //4 KB SPI0 PeripheralType = 11 //4 KB GPIO PeripheralType = 12 //4 KB RTC PeripheralType = 13 //4 KB IOMUX PeripheralType = 14 //4 KB SDIOSlave1 PeripheralType = 15 //4 KB One of three parts UDMA1 PeripheralType = 16 //4 KB I2S0 PeripheralType = 17 //4 KB UART1 PeripheralType = 18 //4 KB I2C0 PeripheralType = 19 //4 KB UDMA0 PeripheralType = 20 //4 KB SDIOSlave2 PeripheralType = 21 //4 KB One of three parts RMT PeripheralType = 22 //4 KB PCNT PeripheralType = 23 //4 KB SDIOSlave3 PeripheralType = 24 //4 KB One of three parts LEDPWM PeripheralType = 25 //4 KB EFuseController PeripheralType = 26 //4 KB FlashEncryption PeripheralType = 27 //4 KB MCPWM0 PeripheralType = 28 //4 KB TIMG0 PeripheralType = 29 //4 KB TIMG1 PeripheralType = 30 //4 KB SPI2 PeripheralType = 31 //4 KB SPI3 PeripheralType = 32 //4 KB SYSCON PeripheralType = 33 //4 KB I2C1 PeripheralType = 34 //4 KB SDMMC PeripheralType = 35 //4 KB EMAC PeripheralType = 36 //8 KB TWAI PeripheralType = 37 //4KB MCPWM1 PeripheralType = 38 //4 KB I2S1 PeripheralType = 39 //4 KB UART2 PeripheralType = 40 //4 KB RNG PeripheralType = 43 //4 KB )
type SysConType ¶
type SysConType byte
const ( SYSCON_SYSCLK_CONF_REG SysConType = 2 // R/W; Configures system clock frequency SYSCON_XTAL_TICK_CONF_REG SysConType = 3 // R/W; Configures the divider value of REF_TICK SYSCON_PLL_TICK_CONF_REG SysConType = 4 // R/W; Configures the divider value of REF_TICK SYSCON_CK8M_TICK_CONF_REG SysConType = 5 // R/W; Configures the divider value of REF_TICK SYSCON_APLL_TICK_CONF_REG SysConType = 6 // R/W; Configures the divider value of REF_TICK SYSCON_DATE_REG SysConType = 7 // R/W; Chip revision register )
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