Documentation
¶
Overview ¶
Package dma provides uniform interface to the DMA controllers.
Index ¶
- Constants
- func AlignOffsets(ptr unsafe.Pointer, size uintptr) (start, end uintptr)
- func MakeSlice[T any](len, cap int) (slice []T)
- func New[T any]() (ptr *T)
- type Channel
- func (c Channel) Clear(ev Event, err Error)
- func (c Channel) Disable()
- func (c Channel) DisableIRQ(ev Event, err Error)
- func (c Channel) Enable()
- func (c Channel) EnableIRQ(ev Event, err Error)
- func (c Channel) Enabled() bool
- func (c Channel) IRQEnabled() (Event, Error)
- func (c Channel) Len() int
- func (c Channel) Prio() Prio
- func (c Channel) SetAddrM(a unsafe.Pointer)
- func (c Channel) SetAddrP(a unsafe.Pointer)
- func (c Channel) SetLen(n int)
- func (c Channel) SetPrio(prio Prio)
- func (c Channel) SetWordSize(p, m uintptr)
- func (c Channel) Setup(m Mode)
- func (c Channel) Status() (Event, Error)
- func (c Channel) WordSize() (p, m uintptr)
- type Controller
- type Error
- type Event
- type Mode
- type Prio
Constants ¶
const CacheMaint = cacheMaint
A CacheMaint indicates whether DMA requires cache maintenance.
const MemAlign = cacheLineSize
An MemAlign is the prefered memory alignment for DMA operations. It's always power of 2 and defined in such a way that a fully MemAlign aligned (top and bottom) memory region corresponds to the complete data cache lines.
Variables ¶
This section is empty.
Functions ¶
func AlignOffsets ¶ added in v0.13.3
AlignOffsets calculatest the start and end offsets to the MemAlign aligned portion of the memory described by ptr and size.
Types ¶
type Channel ¶
type Channel struct {
// contains filtered or unexported fields
}
func (Channel) DisableIRQ ¶
DisableIRQ disables IRQs generation by ev, err.
func (Channel) Enable ¶
func (c Channel) Enable()
Enable enables the channel c. All events and errors should be cleared before call this method.
func (Channel) EnableIRQ ¶
EnableIRQ enables generation of IRQs by ev, err. Documentation does not mention it, but IRQ can be not generated if an event was asserted before enable IRQ for it. So always enable IRQs before channel. Typically, the correct sequence is as follows:
c.Clear(EvAll, ErrAll) c.EnableIRQ(ev, err) c.Enable()
func (Channel) IRQEnabled ¶
IRQEnabled returns events that are enabled to generate interrupt requests.
func (Channel) SetAddrP ¶
SetAddrP sets peripheral address (or memory source address in case of MTM).
func (Channel) SetWordSize ¶
SetWordSize sets the word size (in bytes) for peripheral and memory side of transfer.
type Controller ¶
type Controller struct {
// contains filtered or unexported fields
}
func DMA ¶
func DMA(n int) *Controller
DMA returns n-th DMA controller. The first controller number is 1.
func (*Controller) Channel ¶
func (d *Controller) Channel(sn, rn int) Channel
Channel returns the value that represents the sn stream (F1/Lx DMA channel) together with the connected to it cn request channel (ignored for F1/Lx). Channels with the same sn points to the same DMA stream so they can't be used at the same time.
func (*Controller) DisableClock ¶
func (d *Controller) DisableClock()
DisableClock disables clock to the DMA controller.
func (*Controller) EnableClock ¶
func (d *Controller) EnableClock(lp bool)
EnableClock enables clock to the DMA controller. The lp parameter determines whether the clock remains on in the low power (sleep) mode.
type Error ¶
type Error uint8
const ( ErrTransfer Error = trerr // Transfer Error. ErrDirectMode Error = dmerr // Direct Mode Error. ErrFIFO Error = fferr // FIFO Error. ErrAll = ErrTransfer | ErrDirectMode | ErrFIFO )
type Event ¶
type Event uint8
const ( Complete Event = trce // Transfer Complete Event. HalfComplete Event = htce // Half Transfer Complete Event. EvAll = Complete | HalfComplete )
type Mode ¶
type Mode uint32
const ( PTM Mode = 0 // Read from peripheral, write to memory. MTP Mode = mtp // Read from memory, write to peripheral. MTM Mode = mtm // Read from memory (AddrP), write to memory. Circ Mode = circ // Enable circular mode. IncP Mode = incP // Peripheral increment mode. IncM Mode = incM // Memory increment mode. PFC Mode = pfc // Peripheral flow controller. FT1 Mode = ft1 // FIFO mode, threshold 1/4. FT2 Mode = ft2 // FIFO mode, threshold 2/4. FT3 Mode = ft3 // FIFO mode, threshold 3/4. FT4 Mode = ft4 // FIFO mode, threshold 4/4. TrBuf Mode = trbuf // Bufferable transfers. H7 only, for UART/USART/LPUART. PB4 Mode = pb4 // Peripheral burst transfer, 4 beats. PB8 Mode = pb8 // Peripheral burst transfer, 8 beats. PB16 Mode = pb16 // Peripheral burst transfer, 16 beats. MB4 Mode = mb4 // Memory burst transfer, 4 beats. MB8 Mode = mb4 // Memory burst transfer, 4 beats. MB16 Mode = mb4 // Memory burst transfer, 4 beats. )
Source Files