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Published: Jun 16, 2018 License: MIT Imports: 2 Imported by: 0




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const (
	// DivideByZero occurs when dividing any number by 0 using the DIV or
	// IDIV instruction.
	DivideByZero = InterruptNumber(0)

	// NMI (non-maskable-interrupt) is a hardware interrupt that indicates
	// issues with RAM or unrecoverable hardware problems. It may also be
	// raised by the CPU when a watchdog timer is enabled.
	NMI = InterruptNumber(2)

	// Overflow occurs when an overflow occurs (e.g result of division
	// cannot fit into the registers used).
	Overflow = InterruptNumber(4)

	// BoundRangeExceeded occurs when the BOUND instruction is invoked with
	// an index out of range.
	BoundRangeExceeded = InterruptNumber(5)

	// InvalidOpcode occurs when the CPU attempts to execute an invalid or
	// undefined instruction opcode.
	InvalidOpcode = InterruptNumber(6)

	// DeviceNotAvailable occurs when the CPU attempts to execute an
	// FPU/MMX/SSE instruction while no FPU is available or while
	// FPU/MMX/SSE support has been disabled by manipulating the CR0
	// register.
	DeviceNotAvailable = InterruptNumber(7)

	// DoubleFault occurs when an unhandled exception occurs or when an
	// exception occurs within a running exception handler.
	DoubleFault = InterruptNumber(8)

	// InvalidTSS occurs when the TSS points to an invalid task segment
	// selector.
	InvalidTSS = InterruptNumber(10)

	// SegmentNotPresent occurs when the CPU attempts to invoke a present
	// gate with an invalid stack segment selector.
	SegmentNotPresent = InterruptNumber(11)

	// StackSegmentFault occurs when attempting to push/pop from a
	// non-canonical stack address or when the stack base/limit (set in
	// GDT) checks fail.
	StackSegmentFault = InterruptNumber(12)

	// GPFException occurs when a general protection fault occurs.
	GPFException = InterruptNumber(13)

	// PageFaultException occurs when a page directory table (PDT) or one
	// of its entries is not present or when a privilege and/or RW
	// protection check fails.
	PageFaultException = InterruptNumber(14)

	// FloatingPointException occurs while invoking an FP instruction while:
	//  - CR0.NE = 1 OR
	//  - an unmasked FP exception is pending
	FloatingPointException = InterruptNumber(16)

	// AlignmentCheck occurs when alignment checks are enabled and an
	// unaligmed memory access is performed.
	AlignmentCheck = InterruptNumber(17)

	// MachineCheck occurs when the CPU detects internal errors such as
	// memory-, bus- or cache-related errors.
	MachineCheck = InterruptNumber(18)

	// SIMDFloatingPointException occurs when an unmasked SSE exception
	// occurs while CR4.OSXMMEXCPT is set to 1. If the OSXMMEXCPT bit is
	// not set, SIMD FP exceptions cause InvalidOpcode exceptions instead.
	SIMDFloatingPointException = InterruptNumber(19)


This section is empty.


func HandleInterrupt

func HandleInterrupt(intNumber InterruptNumber, istOffset uint8, handler func(*Registers))

HandleInterrupt ensures that the provided handler will be invoked when a particular interrupt number occurs. The value of the istOffset argument specifies the offset in the interrupt stack table (if 0 then IST is not used).

func Init

func Init()

Init runs the appropriate CPU-specific initialization code for enabling support for interrupt handling.


type InterruptNumber

type InterruptNumber uint8

InterruptNumber describes an x86 interrupt/exception/trap slot.

type Registers

type Registers struct {
	RAX uint64
	RBX uint64
	RCX uint64
	RDX uint64
	RSI uint64
	RDI uint64
	RBP uint64
	R8  uint64
	R9  uint64
	R10 uint64
	R11 uint64
	R12 uint64
	R13 uint64
	R14 uint64
	R15 uint64

	// Info contains the exception code for exceptions, the syscall number
	// for syscall entries or the IRQ number for HW interrupts.
	Info uint64

	// The return frame used by IRETQ
	RIP    uint64
	CS     uint64
	RFlags uint64
	RSP    uint64
	SS     uint64

Registers contains a snapshot of all register values when an exception, interrupt or syscall occurs.

func (*Registers) DumpTo

func (r *Registers) DumpTo(w io.Writer)

DumpTo outputs the register contents to w.

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