rcc

package
v0.0.0-...-3d984ba Latest Latest
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 Go to latest Published: Nov 29, 2018 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package rcc provides interface to Reset and Clock Control.

Peripheral: RCC_Periph Reset and Clock Control. Instances: 

RCC  mmap.RCC_BASE

Registers: 

0x00 32  CR
0x04 32  CFGR
0x08 32  CIR
0x0C 32  APB2RSTR
0x10 32  APB1RSTR
0x14 32  AHBENR
0x18 32  APB2ENR
0x1C 32  APB1ENR
0x20 32  BDCR
0x24 32  CSR

Import: 

stm32/o/f10x_hd/mmap

Index

Constants

View Source 
const (
	HSIONn   = 0
	HSIRDYn  = 1
	HSITRIMn = 3
	HSICALn  = 8
	HSEONn   = 16
	HSERDYn  = 17
	HSEBYPn  = 18
	CSSONn   = 19
	PLLONn   = 24
	PLLRDYn  = 25
)
View Source 
const (
	SWn       = 0
	SWSn      = 2
	HPREn     = 4
	PPRE1n    = 8
	PPRE2n    = 11
	ADCPREn   = 14
	PLLSRCn   = 16
	PLLXTPREn = 17
	PLLMULLn  = 18
	USBPREn   = 22
	MCOn      = 24
)
View Source 
const (
	LSIRDYFn  = 0
	LSERDYFn  = 1
	HSIRDYFn  = 2
	HSERDYFn  = 3
	PLLRDYFn  = 4
	CSSFn     = 7
	LSIRDYIEn = 8
	LSERDYIEn = 9
	HSIRDYIEn = 10
	HSERDYIEn = 11
	PLLRDYIEn = 12
	LSIRDYCn  = 16
	LSERDYCn  = 17
	HSIRDYCn  = 18
	HSERDYCn  = 19
	PLLRDYCn  = 20
	CSSCn     = 23
)
View Source 
const (
	AFIORSTn   = 0
	IOPARSTn   = 2
	IOPBRSTn   = 3
	IOPCRSTn   = 4
	IOPDRSTn   = 5
	ADC1RSTn   = 9
	ADC2RSTn   = 10
	TIM1RSTn   = 11
	SPI1RSTn   = 12
	USART1RSTn = 14
	IOPERSTn   = 6
	IOPFRSTn   = 7
	IOPGRSTn   = 8
	TIM8RSTn   = 13
	ADC3RSTn   = 15
)
View Source 
const (
	TIM2RSTn   = 0
	TIM3RSTn   = 1
	WWDGRSTn   = 11
	USART2RSTn = 17
	I2C1RSTn   = 21
	CAN1RSTn   = 25
	BKPRSTn    = 27
	PWRRSTn    = 28
	TIM4RSTn   = 2
	SPI2RSTn   = 14
	USART3RSTn = 18
	I2C2RSTn   = 22
	USBRSTn    = 23
	TIM5RSTn   = 3
	TIM6RSTn   = 4
	TIM7RSTn   = 5
	SPI3RSTn   = 15
	UART4RSTn  = 19
	UART5RSTn  = 20
	DACRSTn    = 29
)
View Source 
const (
	DMA1ENn  = 0
	SRAMENn  = 2
	FLITFENn = 4
	CRCENn   = 6
	DMA2ENn  = 1
	FSMCENn  = 8
	SDIOENn  = 10
)
View Source 
const (
	AFIOENn   = 0
	IOPAENn   = 2
	IOPBENn   = 3
	IOPCENn   = 4
	IOPDENn   = 5
	ADC1ENn   = 9
	ADC2ENn   = 10
	TIM1ENn   = 11
	SPI1ENn   = 12
	USART1ENn = 14
	IOPEENn   = 6
	IOPFENn   = 7
	IOPGENn   = 8
	TIM8ENn   = 13
	ADC3ENn   = 15
)
View Source 
const (
	TIM2ENn   = 0
	TIM3ENn   = 1
	WWDGENn   = 11
	USART2ENn = 17
	I2C1ENn   = 21
	CAN1ENn   = 25
	BKPENn    = 27
	PWRENn    = 28
	TIM4ENn   = 2
	SPI2ENn   = 14
	USART3ENn = 18
	I2C2ENn   = 22
	USBENn    = 23
	TIM5ENn   = 3
	TIM6ENn   = 4
	TIM7ENn   = 5
	SPI3ENn   = 15
	UART4ENn  = 19
	UART5ENn  = 20
	DACENn    = 29
)
View Source 
const (
	LSEONn  = 0
	LSERDYn = 1
	LSEBYPn = 2
	RTCSELn = 8
	RTCENn  = 15
	BDRSTn  = 16
)
View Source 
const (
	LSIONn    = 0
	LSIRDYn   = 1
	RMVFn     = 24
	PINRSTFn  = 26
	PORRSTFn  = 27
	SFTRSTFn  = 28
	IWDGRSTFn = 29
	WWDGRSTFn = 30
	LPWRRSTFn = 31
)

Variables

View Source 
var RCC = (*RCC_Periph)(unsafe.Pointer(uintptr(mmap.RCC_BASE)))

Functions

This section is empty.

Types

type AHBENR 

type AHBENR uint32
const (
	DMA1EN  AHBENR = 0x01 << 0  //+ DMA1 clock enable.
	SRAMEN  AHBENR = 0x01 << 2  //+ SRAM interface clock enable.
	FLITFEN AHBENR = 0x01 << 4  //+ FLITF clock enable.
	CRCEN   AHBENR = 0x01 << 6  //+ CRC clock enable.
	DMA2EN  AHBENR = 0x01 << 1  //+ DMA2 clock enable.
	FSMCEN  AHBENR = 0x01 << 8  //+ FSMC clock enable.
	SDIOEN  AHBENR = 0x01 << 10 //+ SDIO clock enable.
)

func (AHBENR) Field 

func (b AHBENR) Field(mask AHBENR) int

func (AHBENR) J 

func (mask AHBENR) J(v int) AHBENR

type APB1ENR 

type APB1ENR uint32
const (
	TIM2EN   APB1ENR = 0x01 << 0  //+ Timer 2 clock enabled.
	TIM3EN   APB1ENR = 0x01 << 1  //+ Timer 3 clock enable.
	WWDGEN   APB1ENR = 0x01 << 11 //+ Window Watchdog clock enable.
	USART2EN APB1ENR = 0x01 << 17 //+ USART 2 clock enable.
	I2C1EN   APB1ENR = 0x01 << 21 //+ I2C 1 clock enable.
	CAN1EN   APB1ENR = 0x01 << 25 //+ CAN1 clock enable.
	BKPEN    APB1ENR = 0x01 << 27 //+ Backup interface clock enable.
	PWREN    APB1ENR = 0x01 << 28 //+ Power interface clock enable.
	TIM4EN   APB1ENR = 0x01 << 2  //+ Timer 4 clock enable.
	SPI2EN   APB1ENR = 0x01 << 14 //+ SPI 2 clock enable.
	USART3EN APB1ENR = 0x01 << 18 //+ USART 3 clock enable.
	I2C2EN   APB1ENR = 0x01 << 22 //+ I2C 2 clock enable.
	USBEN    APB1ENR = 0x01 << 23 //+ USB Device clock enable.
	TIM5EN   APB1ENR = 0x01 << 3  //+ Timer 5 clock enable.
	TIM6EN   APB1ENR = 0x01 << 4  //+ Timer 6 clock enable.
	TIM7EN   APB1ENR = 0x01 << 5  //+ Timer 7 clock enable.
	SPI3EN   APB1ENR = 0x01 << 15 //+ SPI 3 clock enable.
	UART4EN  APB1ENR = 0x01 << 19 //+ UART 4 clock enable.
	UART5EN  APB1ENR = 0x01 << 20 //+ UART 5 clock enable.
	DACEN    APB1ENR = 0x01 << 29 //+ DAC interface clock enable.
)

func (APB1ENR) Field 

func (b APB1ENR) Field(mask APB1ENR) int

func (APB1ENR) J 

func (mask APB1ENR) J(v int) APB1ENR

type APB1RSTR 

type APB1RSTR uint32
const (
	TIM2RST   APB1RSTR = 0x01 << 0  //+ Timer 2 reset.
	TIM3RST   APB1RSTR = 0x01 << 1  //+ Timer 3 reset.
	WWDGRST   APB1RSTR = 0x01 << 11 //+ Window Watchdog reset.
	USART2RST APB1RSTR = 0x01 << 17 //+ USART 2 reset.
	I2C1RST   APB1RSTR = 0x01 << 21 //+ I2C 1 reset.
	CAN1RST   APB1RSTR = 0x01 << 25 //+ CAN1 reset.
	BKPRST    APB1RSTR = 0x01 << 27 //+ Backup interface reset.
	PWRRST    APB1RSTR = 0x01 << 28 //+ Power interface reset.
	TIM4RST   APB1RSTR = 0x01 << 2  //+ Timer 4 reset.
	SPI2RST   APB1RSTR = 0x01 << 14 //+ SPI 2 reset.
	USART3RST APB1RSTR = 0x01 << 18 //+ USART 3 reset.
	I2C2RST   APB1RSTR = 0x01 << 22 //+ I2C 2 reset.
	USBRST    APB1RSTR = 0x01 << 23 //+ USB Device reset.
	TIM5RST   APB1RSTR = 0x01 << 3  //+ Timer 5 reset.
	TIM6RST   APB1RSTR = 0x01 << 4  //+ Timer 6 reset.
	TIM7RST   APB1RSTR = 0x01 << 5  //+ Timer 7 reset.
	SPI3RST   APB1RSTR = 0x01 << 15 //+ SPI 3 reset.
	UART4RST  APB1RSTR = 0x01 << 19 //+ UART 4 reset.
	UART5RST  APB1RSTR = 0x01 << 20 //+ UART 5 reset.
	DACRST    APB1RSTR = 0x01 << 29 //+ DAC interface reset.
)

func (APB1RSTR) Field 

func (b APB1RSTR) Field(mask APB1RSTR) int

func (APB1RSTR) J 

func (mask APB1RSTR) J(v int) APB1RSTR

type APB2ENR 

type APB2ENR uint32
const (
	AFIOEN   APB2ENR = 0x01 << 0  //+ Alternate Function I/O clock enable.
	IOPAEN   APB2ENR = 0x01 << 2  //+ I/O port A clock enable.
	IOPBEN   APB2ENR = 0x01 << 3  //+ I/O port B clock enable.
	IOPCEN   APB2ENR = 0x01 << 4  //+ I/O port C clock enable.
	IOPDEN   APB2ENR = 0x01 << 5  //+ I/O port D clock enable.
	ADC1EN   APB2ENR = 0x01 << 9  //+ ADC 1 interface clock enable.
	ADC2EN   APB2ENR = 0x01 << 10 //+ ADC 2 interface clock enable.
	TIM1EN   APB2ENR = 0x01 << 11 //+ TIM1 Timer clock enable.
	SPI1EN   APB2ENR = 0x01 << 12 //+ SPI 1 clock enable.
	USART1EN APB2ENR = 0x01 << 14 //+ USART1 clock enable.
	IOPEEN   APB2ENR = 0x01 << 6  //+ I/O port E clock enable.
	IOPFEN   APB2ENR = 0x01 << 7  //+ I/O port F clock enable.
	IOPGEN   APB2ENR = 0x01 << 8  //+ I/O port G clock enable.
	TIM8EN   APB2ENR = 0x01 << 13 //+ TIM8 Timer clock enable.
	ADC3EN   APB2ENR = 0x01 << 15 //+ DMA1 clock enable.
)

func (APB2ENR) Field 

func (b APB2ENR) Field(mask APB2ENR) int

func (APB2ENR) J 

func (mask APB2ENR) J(v int) APB2ENR

type APB2RSTR 

type APB2RSTR uint32
const (
	AFIORST   APB2RSTR = 0x01 << 0  //+ Alternate Function I/O reset.
	IOPARST   APB2RSTR = 0x01 << 2  //+ I/O port A reset.
	IOPBRST   APB2RSTR = 0x01 << 3  //+ I/O port B reset.
	IOPCRST   APB2RSTR = 0x01 << 4  //+ I/O port C reset.
	IOPDRST   APB2RSTR = 0x01 << 5  //+ I/O port D reset.
	ADC1RST   APB2RSTR = 0x01 << 9  //+ ADC 1 interface reset.
	ADC2RST   APB2RSTR = 0x01 << 10 //+ ADC 2 interface reset.
	TIM1RST   APB2RSTR = 0x01 << 11 //+ TIM1 Timer reset.
	SPI1RST   APB2RSTR = 0x01 << 12 //+ SPI 1 reset.
	USART1RST APB2RSTR = 0x01 << 14 //+ USART1 reset.
	IOPERST   APB2RSTR = 0x01 << 6  //+ I/O port E reset.
	IOPFRST   APB2RSTR = 0x01 << 7  //+ I/O port F reset.
	IOPGRST   APB2RSTR = 0x01 << 8  //+ I/O port G reset.
	TIM8RST   APB2RSTR = 0x01 << 13 //+ TIM8 Timer reset.
	ADC3RST   APB2RSTR = 0x01 << 15 //+ ADC3 interface reset.
)

func (APB2RSTR) Field 

func (b APB2RSTR) Field(mask APB2RSTR) int

func (APB2RSTR) J 

func (mask APB2RSTR) J(v int) APB2RSTR

type BDCR 

type BDCR uint32
const (
	LSEON          BDCR = 0x01 << 0  //+ External Low Speed oscillator enable.
	LSERDY         BDCR = 0x01 << 1  //+ External Low Speed oscillator Ready.
	LSEBYP         BDCR = 0x01 << 2  //+ External Low Speed oscillator Bypass.
	RTCSEL         BDCR = 0x03 << 8  //+ RTCSEL[1:0] bits (RTC clock source selection).
	RTCSEL_0       BDCR = 0x01 << 8  //  Bit 0.
	RTCSEL_1       BDCR = 0x02 << 8  //  Bit 1.
	RTCSEL_NOCLOCK BDCR = 0x00 << 8  //  No clock.
	RTCSEL_LSE     BDCR = 0x01 << 8  //  LSE oscillator clock used as RTC clock.
	RTCSEL_LSI     BDCR = 0x02 << 8  //  LSI oscillator clock used as RTC clock.
	RTCSEL_HSE     BDCR = 0x03 << 8  //  HSE oscillator clock divided by 128 used as RTC clock.
	RTCEN          BDCR = 0x01 << 15 //+ RTC clock enable.
	BDRST          BDCR = 0x01 << 16 //+ Backup domain software reset.
)

func (BDCR) Field 

func (b BDCR) Field(mask BDCR) int

func (BDCR) J 

func (mask BDCR) J(v int) BDCR

type CFGR 

type CFGR uint32
const (
	SW                CFGR = 0x03 << 0  //+ SW[1:0] bits (System clock Switch).
	SW_0              CFGR = 0x01 << 0  //  Bit 0.
	SW_1              CFGR = 0x02 << 0  //  Bit 1.
	SW_HSI            CFGR = 0x00 << 0  //  HSI selected as system clock.
	SW_HSE            CFGR = 0x01 << 0  //  HSE selected as system clock.
	SW_PLL            CFGR = 0x02 << 0  //  PLL selected as system clock.
	SWS               CFGR = 0x03 << 2  //+ SWS[1:0] bits (System Clock Switch Status).
	SWS_0             CFGR = 0x01 << 2  //  Bit 0.
	SWS_1             CFGR = 0x02 << 2  //  Bit 1.
	SWS_HSI           CFGR = 0x00 << 2  //  HSI oscillator used as system clock.
	SWS_HSE           CFGR = 0x01 << 2  //  HSE oscillator used as system clock.
	SWS_PLL           CFGR = 0x02 << 2  //  PLL used as system clock.
	HPRE              CFGR = 0x0F << 4  //+ HPRE[3:0] bits (AHB prescaler).
	HPRE_0            CFGR = 0x01 << 4  //  Bit 0.
	HPRE_1            CFGR = 0x02 << 4  //  Bit 1.
	HPRE_2            CFGR = 0x04 << 4  //  Bit 2.
	HPRE_3            CFGR = 0x08 << 4  //  Bit 3.
	HPRE_DIV1         CFGR = 0x00 << 4  //  SYSCLK not divided.
	HPRE_DIV2         CFGR = 0x08 << 4  //  SYSCLK divided by 2.
	HPRE_DIV4         CFGR = 0x09 << 4  //  SYSCLK divided by 4.
	HPRE_DIV8         CFGR = 0x0A << 4  //  SYSCLK divided by 8.
	HPRE_DIV16        CFGR = 0x0B << 4  //  SYSCLK divided by 16.
	HPRE_DIV64        CFGR = 0x0C << 4  //  SYSCLK divided by 64.
	HPRE_DIV128       CFGR = 0x0D << 4  //  SYSCLK divided by 128.
	HPRE_DIV256       CFGR = 0x0E << 4  //  SYSCLK divided by 256.
	HPRE_DIV512       CFGR = 0x0F << 4  //  SYSCLK divided by 512.
	PPRE1             CFGR = 0x07 << 8  //+ PRE1[2:0] bits (APB1 prescaler).
	PPRE1_0           CFGR = 0x01 << 8  //  Bit 0.
	PPRE1_1           CFGR = 0x02 << 8  //  Bit 1.
	PPRE1_2           CFGR = 0x04 << 8  //  Bit 2.
	PPRE1_DIV1        CFGR = 0x00 << 8  //  HCLK not divided.
	PPRE1_DIV2        CFGR = 0x04 << 8  //  HCLK divided by 2.
	PPRE1_DIV4        CFGR = 0x05 << 8  //  HCLK divided by 4.
	PPRE1_DIV8        CFGR = 0x06 << 8  //  HCLK divided by 8.
	PPRE1_DIV16       CFGR = 0x07 << 8  //  HCLK divided by 16.
	PPRE2             CFGR = 0x07 << 11 //+ PRE2[2:0] bits (APB2 prescaler).
	PPRE2_0           CFGR = 0x01 << 11 //  Bit 0.
	PPRE2_1           CFGR = 0x02 << 11 //  Bit 1.
	PPRE2_2           CFGR = 0x04 << 11 //  Bit 2.
	PPRE2_DIV1        CFGR = 0x00 << 11 //  HCLK not divided.
	PPRE2_DIV2        CFGR = 0x04 << 11 //  HCLK divided by 2.
	PPRE2_DIV4        CFGR = 0x05 << 11 //  HCLK divided by 4.
	PPRE2_DIV8        CFGR = 0x06 << 11 //  HCLK divided by 8.
	PPRE2_DIV16       CFGR = 0x07 << 11 //  HCLK divided by 16.
	ADCPRE            CFGR = 0x03 << 14 //+ ADCPRE[1:0] bits (ADC prescaler).
	ADCPRE_0          CFGR = 0x01 << 14 //  Bit 0.
	ADCPRE_1          CFGR = 0x02 << 14 //  Bit 1.
	ADCPRE_DIV2       CFGR = 0x00 << 14 //  PCLK2 divided by 2.
	ADCPRE_DIV4       CFGR = 0x01 << 14 //  PCLK2 divided by 4.
	ADCPRE_DIV6       CFGR = 0x02 << 14 //  PCLK2 divided by 6.
	ADCPRE_DIV8       CFGR = 0x03 << 14 //  PCLK2 divided by 8.
	PLLSRC            CFGR = 0x01 << 16 //+ PLL entry clock source.
	PLLXTPRE          CFGR = 0x01 << 17 //+ HSE divider for PLL entry.
	PLLMULL           CFGR = 0x0F << 18 //+ PLLMUL[3:0] bits (PLL multiplication factor).
	PLLMULL_0         CFGR = 0x01 << 18 //  Bit 0.
	PLLMULL_1         CFGR = 0x02 << 18 //  Bit 1.
	PLLMULL_2         CFGR = 0x04 << 18 //  Bit 2.
	PLLMULL_3         CFGR = 0x08 << 18 //  Bit 3.
	PLLSRC_HSI_Div2   CFGR = 0x00 << 18 //  HSI clock divided by 2 selected as PLL entry clock source.
	PLLSRC_HSE        CFGR = 0x01 << 16 //  HSE clock selected as PLL entry clock source.
	PLLXTPRE_HSE      CFGR = 0x00 << 18 //  HSE clock not divided for PLL entry.
	PLLXTPRE_HSE_Div2 CFGR = 0x01 << 17 //  HSE clock divided by 2 for PLL entry.
	PLLMULL2          CFGR = 0x00 << 18 //  PLL input clock*2.
	PLLMULL3          CFGR = 0x01 << 18 //  PLL input clock*3.
	PLLMULL4          CFGR = 0x02 << 18 //  PLL input clock*4.
	PLLMULL5          CFGR = 0x03 << 18 //  PLL input clock*5.
	PLLMULL6          CFGR = 0x04 << 18 //  PLL input clock*6.
	PLLMULL7          CFGR = 0x05 << 18 //  PLL input clock*7.
	PLLMULL8          CFGR = 0x06 << 18 //  PLL input clock*8.
	PLLMULL9          CFGR = 0x07 << 18 //  PLL input clock*9.
	PLLMULL10         CFGR = 0x08 << 18 //  PLL input clock10.
	PLLMULL11         CFGR = 0x09 << 18 //  PLL input clock*11.
	PLLMULL12         CFGR = 0x0A << 18 //  PLL input clock*12.
	PLLMULL13         CFGR = 0x0B << 18 //  PLL input clock*13.
	PLLMULL14         CFGR = 0x0C << 18 //  PLL input clock*14.
	PLLMULL15         CFGR = 0x0D << 18 //  PLL input clock*15.
	PLLMULL16         CFGR = 0x0E << 18 //  PLL input clock*16.
	USBPRE            CFGR = 0x01 << 22 //+ USB Device prescaler.
	MCO               CFGR = 0x07 << 24 //+ MCO[2:0] bits (Microcontroller Clock Output).
	MCO_0             CFGR = 0x01 << 24 //  Bit 0.
	MCO_1             CFGR = 0x02 << 24 //  Bit 1.
	MCO_2             CFGR = 0x04 << 24 //  Bit 2.
	MCO_NOCLOCK       CFGR = 0x00 << 24 //  No clock.
	MCO_SYSCLK        CFGR = 0x04 << 24 //  System clock selected as MCO source.
	MCO_HSI           CFGR = 0x05 << 24 //  HSI clock selected as MCO source.
	MCO_HSE           CFGR = 0x06 << 24 //  HSE clock selected as MCO source.
	MCO_PLL           CFGR = 0x07 << 24 //  PLL clock divided by 2 selected as MCO source.
)

func (CFGR) Field 

func (b CFGR) Field(mask CFGR) int

func (CFGR) J 

func (mask CFGR) J(v int) CFGR

type CIR 

type CIR uint32
const (
	LSIRDYF  CIR = 0x01 << 0  //+ LSI Ready Interrupt flag.
	LSERDYF  CIR = 0x01 << 1  //+ LSE Ready Interrupt flag.
	HSIRDYF  CIR = 0x01 << 2  //+ HSI Ready Interrupt flag.
	HSERDYF  CIR = 0x01 << 3  //+ HSE Ready Interrupt flag.
	PLLRDYF  CIR = 0x01 << 4  //+ PLL Ready Interrupt flag.
	CSSF     CIR = 0x01 << 7  //+ Clock Security System Interrupt flag.
	LSIRDYIE CIR = 0x01 << 8  //+ LSI Ready Interrupt Enable.
	LSERDYIE CIR = 0x01 << 9  //+ LSE Ready Interrupt Enable.
	HSIRDYIE CIR = 0x01 << 10 //+ HSI Ready Interrupt Enable.
	HSERDYIE CIR = 0x01 << 11 //+ HSE Ready Interrupt Enable.
	PLLRDYIE CIR = 0x01 << 12 //+ PLL Ready Interrupt Enable.
	LSIRDYC  CIR = 0x01 << 16 //+ LSI Ready Interrupt Clear.
	LSERDYC  CIR = 0x01 << 17 //+ LSE Ready Interrupt Clear.
	HSIRDYC  CIR = 0x01 << 18 //+ HSI Ready Interrupt Clear.
	HSERDYC  CIR = 0x01 << 19 //+ HSE Ready Interrupt Clear.
	PLLRDYC  CIR = 0x01 << 20 //+ PLL Ready Interrupt Clear.
	CSSC     CIR = 0x01 << 23 //+ Clock Security System Interrupt Clear.
)

func (CIR) Field 

func (b CIR) Field(mask CIR) int

func (CIR) J 

func (mask CIR) J(v int) CIR

type CR 

type CR uint32
const (
	HSION   CR = 0x01 << 0  //+ Internal High Speed clock enable.
	HSIRDY  CR = 0x01 << 1  //+ Internal High Speed clock ready flag.
	HSITRIM CR = 0x1F << 3  //+ Internal High Speed clock trimming.
	HSICAL  CR = 0xFF << 8  //+ Internal High Speed clock Calibration.
	HSEON   CR = 0x01 << 16 //+ External High Speed clock enable.
	HSERDY  CR = 0x01 << 17 //+ External High Speed clock ready flag.
	HSEBYP  CR = 0x01 << 18 //+ External High Speed clock Bypass.
	CSSON   CR = 0x01 << 19 //+ Clock Security System enable.
	PLLON   CR = 0x01 << 24 //+ PLL enable.
	PLLRDY  CR = 0x01 << 25 //+ PLL clock ready flag.
)

func (CR) Field 

func (b CR) Field(mask CR) int

func (CR) J 

func (mask CR) J(v int) CR

type CSR 

type CSR uint32
const (
	LSION    CSR = 0x01 << 0  //+ Internal Low Speed oscillator enable.
	LSIRDY   CSR = 0x01 << 1  //+ Internal Low Speed oscillator Ready.
	RMVF     CSR = 0x01 << 24 //+ Remove reset flag.
	PINRSTF  CSR = 0x01 << 26 //+ PIN reset flag.
	PORRSTF  CSR = 0x01 << 27 //+ POR/PDR reset flag.
	SFTRSTF  CSR = 0x01 << 28 //+ Software Reset flag.
	IWDGRSTF CSR = 0x01 << 29 //+ Independent Watchdog reset flag.
	WWDGRSTF CSR = 0x01 << 30 //+ Window watchdog reset flag.
	LPWRRSTF CSR = 0x01 << 31 //+ Low-Power reset flag.
)

func (CSR) Field 

func (b CSR) Field(mask CSR) int

func (CSR) J 

func (mask CSR) J(v int) CSR

type RAHBENR 

type RAHBENR struct{ mmio.U32 }

func (*RAHBENR) AtomicClearBits 

func (r *RAHBENR) AtomicClearBits(mask AHBENR)

func (*RAHBENR) AtomicSetBits 

func (r *RAHBENR) AtomicSetBits(mask AHBENR)

func (*RAHBENR) AtomicStoreBits 

func (r *RAHBENR) AtomicStoreBits(mask, b AHBENR)

func (*RAHBENR) Bits 

func (r *RAHBENR) Bits(mask AHBENR) AHBENR

func (*RAHBENR) ClearBits 

func (r *RAHBENR) ClearBits(mask AHBENR)

func (*RAHBENR) Load 

func (r *RAHBENR) Load() AHBENR

func (*RAHBENR) SetBits 

func (r *RAHBENR) SetBits(mask AHBENR)

func (*RAHBENR) Store 

func (r *RAHBENR) Store(b AHBENR)

func (*RAHBENR) StoreBits 

func (r *RAHBENR) StoreBits(mask, b AHBENR)

type RAPB1ENR 

type RAPB1ENR struct{ mmio.U32 }

func (*RAPB1ENR) AtomicClearBits 

func (r *RAPB1ENR) AtomicClearBits(mask APB1ENR)

func (*RAPB1ENR) AtomicSetBits 

func (r *RAPB1ENR) AtomicSetBits(mask APB1ENR)

func (*RAPB1ENR) AtomicStoreBits 

func (r *RAPB1ENR) AtomicStoreBits(mask, b APB1ENR)

func (*RAPB1ENR) Bits 

func (r *RAPB1ENR) Bits(mask APB1ENR) APB1ENR

func (*RAPB1ENR) ClearBits 

func (r *RAPB1ENR) ClearBits(mask APB1ENR)

func (*RAPB1ENR) Load 

func (r *RAPB1ENR) Load() APB1ENR

func (*RAPB1ENR) SetBits 

func (r *RAPB1ENR) SetBits(mask APB1ENR)

func (*RAPB1ENR) Store 

func (r *RAPB1ENR) Store(b APB1ENR)

func (*RAPB1ENR) StoreBits 

func (r *RAPB1ENR) StoreBits(mask, b APB1ENR)

type RAPB1RSTR 

type RAPB1RSTR struct{ mmio.U32 }

func (*RAPB1RSTR) AtomicClearBits 

func (r *RAPB1RSTR) AtomicClearBits(mask APB1RSTR)

func (*RAPB1RSTR) AtomicSetBits 

func (r *RAPB1RSTR) AtomicSetBits(mask APB1RSTR)

func (*RAPB1RSTR) AtomicStoreBits 

func (r *RAPB1RSTR) AtomicStoreBits(mask, b APB1RSTR)

func (*RAPB1RSTR) Bits 

func (r *RAPB1RSTR) Bits(mask APB1RSTR) APB1RSTR

func (*RAPB1RSTR) ClearBits 

func (r *RAPB1RSTR) ClearBits(mask APB1RSTR)

func (*RAPB1RSTR) Load 

func (r *RAPB1RSTR) Load() APB1RSTR

func (*RAPB1RSTR) SetBits 

func (r *RAPB1RSTR) SetBits(mask APB1RSTR)

func (*RAPB1RSTR) Store 

func (r *RAPB1RSTR) Store(b APB1RSTR)

func (*RAPB1RSTR) StoreBits 

func (r *RAPB1RSTR) StoreBits(mask, b APB1RSTR)

type RAPB2ENR 

type RAPB2ENR struct{ mmio.U32 }

func (*RAPB2ENR) AtomicClearBits 

func (r *RAPB2ENR) AtomicClearBits(mask APB2ENR)

func (*RAPB2ENR) AtomicSetBits 

func (r *RAPB2ENR) AtomicSetBits(mask APB2ENR)

func (*RAPB2ENR) AtomicStoreBits 

func (r *RAPB2ENR) AtomicStoreBits(mask, b APB2ENR)

func (*RAPB2ENR) Bits 

func (r *RAPB2ENR) Bits(mask APB2ENR) APB2ENR

func (*RAPB2ENR) ClearBits 

func (r *RAPB2ENR) ClearBits(mask APB2ENR)

func (*RAPB2ENR) Load 

func (r *RAPB2ENR) Load() APB2ENR

func (*RAPB2ENR) SetBits 

func (r *RAPB2ENR) SetBits(mask APB2ENR)

func (*RAPB2ENR) Store 

func (r *RAPB2ENR) Store(b APB2ENR)

func (*RAPB2ENR) StoreBits 

func (r *RAPB2ENR) StoreBits(mask, b APB2ENR)

type RAPB2RSTR 

type RAPB2RSTR struct{ mmio.U32 }

func (*RAPB2RSTR) AtomicClearBits 

func (r *RAPB2RSTR) AtomicClearBits(mask APB2RSTR)

func (*RAPB2RSTR) AtomicSetBits 

func (r *RAPB2RSTR) AtomicSetBits(mask APB2RSTR)

func (*RAPB2RSTR) AtomicStoreBits 

func (r *RAPB2RSTR) AtomicStoreBits(mask, b APB2RSTR)

func (*RAPB2RSTR) Bits 

func (r *RAPB2RSTR) Bits(mask APB2RSTR) APB2RSTR

func (*RAPB2RSTR) ClearBits 

func (r *RAPB2RSTR) ClearBits(mask APB2RSTR)

func (*RAPB2RSTR) Load 

func (r *RAPB2RSTR) Load() APB2RSTR

func (*RAPB2RSTR) SetBits 

func (r *RAPB2RSTR) SetBits(mask APB2RSTR)

func (*RAPB2RSTR) Store 

func (r *RAPB2RSTR) Store(b APB2RSTR)

func (*RAPB2RSTR) StoreBits 

func (r *RAPB2RSTR) StoreBits(mask, b APB2RSTR)

type RBDCR 

type RBDCR struct{ mmio.U32 }

func (*RBDCR) AtomicClearBits 

func (r *RBDCR) AtomicClearBits(mask BDCR)

func (*RBDCR) AtomicSetBits 

func (r *RBDCR) AtomicSetBits(mask BDCR)

func (*RBDCR) AtomicStoreBits 

func (r *RBDCR) AtomicStoreBits(mask, b BDCR)

func (*RBDCR) Bits 

func (r *RBDCR) Bits(mask BDCR) BDCR

func (*RBDCR) ClearBits 

func (r *RBDCR) ClearBits(mask BDCR)

func (*RBDCR) Load 

func (r *RBDCR) Load() BDCR

func (*RBDCR) SetBits 

func (r *RBDCR) SetBits(mask BDCR)

func (*RBDCR) Store 

func (r *RBDCR) Store(b BDCR)

func (*RBDCR) StoreBits 

func (r *RBDCR) StoreBits(mask, b BDCR)

type RCC_Periph 

type RCC_Periph struct {
	CR       RCR
	CFGR     RCFGR
	CIR      RCIR
	APB2RSTR RAPB2RSTR
	APB1RSTR RAPB1RSTR
	AHBENR   RAHBENR
	APB2ENR  RAPB2ENR
	APB1ENR  RAPB1ENR
	BDCR     RBDCR
	CSR      RCSR
}

func (*RCC_Periph) ADC1EN 

func (p *RCC_Periph) ADC1EN() RMAPB2ENR

func (*RCC_Periph) ADC1RST 

func (p *RCC_Periph) ADC1RST() RMAPB2RSTR

func (*RCC_Periph) ADC2EN 

func (p *RCC_Periph) ADC2EN() RMAPB2ENR

func (*RCC_Periph) ADC2RST 

func (p *RCC_Periph) ADC2RST() RMAPB2RSTR

func (*RCC_Periph) ADC3EN 

func (p *RCC_Periph) ADC3EN() RMAPB2ENR

func (*RCC_Periph) ADC3RST 

func (p *RCC_Periph) ADC3RST() RMAPB2RSTR

func (*RCC_Periph) ADCPRE 

func (p *RCC_Periph) ADCPRE() RMCFGR

func (*RCC_Periph) AFIOEN 

func (p *RCC_Periph) AFIOEN() RMAPB2ENR

func (*RCC_Periph) AFIORST 

func (p *RCC_Periph) AFIORST() RMAPB2RSTR

func (*RCC_Periph) BDRST 

func (p *RCC_Periph) BDRST() RMBDCR

func (*RCC_Periph) BKPEN 

func (p *RCC_Periph) BKPEN() RMAPB1ENR

func (*RCC_Periph) BKPRST 

func (p *RCC_Periph) BKPRST() RMAPB1RSTR

func (*RCC_Periph) BaseAddr 

func (p *RCC_Periph) BaseAddr() uintptr

func (*RCC_Periph) CAN1EN 

func (p *RCC_Periph) CAN1EN() RMAPB1ENR

func (*RCC_Periph) CAN1RST 

func (p *RCC_Periph) CAN1RST() RMAPB1RSTR

func (*RCC_Periph) CRCEN 

func (p *RCC_Periph) CRCEN() RMAHBENR

func (*RCC_Periph) CSSC 

func (p *RCC_Periph) CSSC() RMCIR

func (*RCC_Periph) CSSF 

func (p *RCC_Periph) CSSF() RMCIR

func (*RCC_Periph) CSSON 

func (p *RCC_Periph) CSSON() RMCR

func (*RCC_Periph) DACEN 

func (p *RCC_Periph) DACEN() RMAPB1ENR

func (*RCC_Periph) DACRST 

func (p *RCC_Periph) DACRST() RMAPB1RSTR

func (*RCC_Periph) DMA1EN 

func (p *RCC_Periph) DMA1EN() RMAHBENR

func (*RCC_Periph) DMA2EN 

func (p *RCC_Periph) DMA2EN() RMAHBENR

func (*RCC_Periph) FLITFEN 

func (p *RCC_Periph) FLITFEN() RMAHBENR

func (*RCC_Periph) FSMCEN 

func (p *RCC_Periph) FSMCEN() RMAHBENR

func (*RCC_Periph) HPRE 

func (p *RCC_Periph) HPRE() RMCFGR

func (*RCC_Periph) HSEBYP 

func (p *RCC_Periph) HSEBYP() RMCR

func (*RCC_Periph) HSEON 

func (p *RCC_Periph) HSEON() RMCR

func (*RCC_Periph) HSERDY 

func (p *RCC_Periph) HSERDY() RMCR

func (*RCC_Periph) HSERDYC 

func (p *RCC_Periph) HSERDYC() RMCIR

func (*RCC_Periph) HSERDYF 

func (p *RCC_Periph) HSERDYF() RMCIR

func (*RCC_Periph) HSERDYIE 

func (p *RCC_Periph) HSERDYIE() RMCIR

func (*RCC_Periph) HSICAL 

func (p *RCC_Periph) HSICAL() RMCR

func (*RCC_Periph) HSION 

func (p *RCC_Periph) HSION() RMCR

func (*RCC_Periph) HSIRDY 

func (p *RCC_Periph) HSIRDY() RMCR

func (*RCC_Periph) HSIRDYC 

func (p *RCC_Periph) HSIRDYC() RMCIR

func (*RCC_Periph) HSIRDYF 

func (p *RCC_Periph) HSIRDYF() RMCIR

func (*RCC_Periph) HSIRDYIE 

func (p *RCC_Periph) HSIRDYIE() RMCIR

func (*RCC_Periph) HSITRIM 

func (p *RCC_Periph) HSITRIM() RMCR

func (*RCC_Periph) I2C1EN 

func (p *RCC_Periph) I2C1EN() RMAPB1ENR

func (*RCC_Periph) I2C1RST 

func (p *RCC_Periph) I2C1RST() RMAPB1RSTR

func (*RCC_Periph) I2C2EN 

func (p *RCC_Periph) I2C2EN() RMAPB1ENR

func (*RCC_Periph) I2C2RST 

func (p *RCC_Periph) I2C2RST() RMAPB1RSTR

func (*RCC_Periph) IOPAEN 

func (p *RCC_Periph) IOPAEN() RMAPB2ENR

func (*RCC_Periph) IOPARST 

func (p *RCC_Periph) IOPARST() RMAPB2RSTR

func (*RCC_Periph) IOPBEN 

func (p *RCC_Periph) IOPBEN() RMAPB2ENR

func (*RCC_Periph) IOPBRST 

func (p *RCC_Periph) IOPBRST() RMAPB2RSTR

func (*RCC_Periph) IOPCEN 

func (p *RCC_Periph) IOPCEN() RMAPB2ENR

func (*RCC_Periph) IOPCRST 

func (p *RCC_Periph) IOPCRST() RMAPB2RSTR

func (*RCC_Periph) IOPDEN 

func (p *RCC_Periph) IOPDEN() RMAPB2ENR

func (*RCC_Periph) IOPDRST 

func (p *RCC_Periph) IOPDRST() RMAPB2RSTR

func (*RCC_Periph) IOPEEN 

func (p *RCC_Periph) IOPEEN() RMAPB2ENR

func (*RCC_Periph) IOPERST 

func (p *RCC_Periph) IOPERST() RMAPB2RSTR

func (*RCC_Periph) IOPFEN 

func (p *RCC_Periph) IOPFEN() RMAPB2ENR

func (*RCC_Periph) IOPFRST 

func (p *RCC_Periph) IOPFRST() RMAPB2RSTR

func (*RCC_Periph) IOPGEN 

func (p *RCC_Periph) IOPGEN() RMAPB2ENR

func (*RCC_Periph) IOPGRST 

func (p *RCC_Periph) IOPGRST() RMAPB2RSTR

func (*RCC_Periph) IWDGRSTF 

func (p *RCC_Periph) IWDGRSTF() RMCSR

func (*RCC_Periph) LPWRRSTF 

func (p *RCC_Periph) LPWRRSTF() RMCSR

func (*RCC_Periph) LSEBYP 

func (p *RCC_Periph) LSEBYP() RMBDCR

func (*RCC_Periph) LSEON 

func (p *RCC_Periph) LSEON() RMBDCR

func (*RCC_Periph) LSERDY 

func (p *RCC_Periph) LSERDY() RMBDCR

func (*RCC_Periph) LSERDYC 

func (p *RCC_Periph) LSERDYC() RMCIR

func (*RCC_Periph) LSERDYF 

func (p *RCC_Periph) LSERDYF() RMCIR

func (*RCC_Periph) LSERDYIE 

func (p *RCC_Periph) LSERDYIE() RMCIR

func (*RCC_Periph) LSION 

func (p *RCC_Periph) LSION() RMCSR

func (*RCC_Periph) LSIRDY 

func (p *RCC_Periph) LSIRDY() RMCSR

func (*RCC_Periph) LSIRDYC 

func (p *RCC_Periph) LSIRDYC() RMCIR

func (*RCC_Periph) LSIRDYF 

func (p *RCC_Periph) LSIRDYF() RMCIR

func (*RCC_Periph) LSIRDYIE 

func (p *RCC_Periph) LSIRDYIE() RMCIR

func (*RCC_Periph) MCO 

func (p *RCC_Periph) MCO() RMCFGR

func (*RCC_Periph) PINRSTF 

func (p *RCC_Periph) PINRSTF() RMCSR

func (*RCC_Periph) PLLMULL 

func (p *RCC_Periph) PLLMULL() RMCFGR

func (*RCC_Periph) PLLON 

func (p *RCC_Periph) PLLON() RMCR

func (*RCC_Periph) PLLRDY 

func (p *RCC_Periph) PLLRDY() RMCR

func (*RCC_Periph) PLLRDYC 

func (p *RCC_Periph) PLLRDYC() RMCIR

func (*RCC_Periph) PLLRDYF 

func (p *RCC_Periph) PLLRDYF() RMCIR

func (*RCC_Periph) PLLRDYIE 

func (p *RCC_Periph) PLLRDYIE() RMCIR

func (*RCC_Periph) PLLSRC 

func (p *RCC_Periph) PLLSRC() RMCFGR

func (*RCC_Periph) PLLXTPRE 

func (p *RCC_Periph) PLLXTPRE() RMCFGR

func (*RCC_Periph) PORRSTF 

func (p *RCC_Periph) PORRSTF() RMCSR

func (*RCC_Periph) PPRE1 

func (p *RCC_Periph) PPRE1() RMCFGR

func (*RCC_Periph) PPRE2 

func (p *RCC_Periph) PPRE2() RMCFGR

func (*RCC_Periph) PWREN 

func (p *RCC_Periph) PWREN() RMAPB1ENR

func (*RCC_Periph) PWRRST 

func (p *RCC_Periph) PWRRST() RMAPB1RSTR

func (*RCC_Periph) RMVF 

func (p *RCC_Periph) RMVF() RMCSR

func (*RCC_Periph) RTCEN 

func (p *RCC_Periph) RTCEN() RMBDCR

func (*RCC_Periph) RTCSEL 

func (p *RCC_Periph) RTCSEL() RMBDCR

func (*RCC_Periph) SDIOEN 

func (p *RCC_Periph) SDIOEN() RMAHBENR

func (*RCC_Periph) SFTRSTF 

func (p *RCC_Periph) SFTRSTF() RMCSR

func (*RCC_Periph) SPI1EN 

func (p *RCC_Periph) SPI1EN() RMAPB2ENR

func (*RCC_Periph) SPI1RST 

func (p *RCC_Periph) SPI1RST() RMAPB2RSTR

func (*RCC_Periph) SPI2EN 

func (p *RCC_Periph) SPI2EN() RMAPB1ENR

func (*RCC_Periph) SPI2RST 

func (p *RCC_Periph) SPI2RST() RMAPB1RSTR

func (*RCC_Periph) SPI3EN 

func (p *RCC_Periph) SPI3EN() RMAPB1ENR

func (*RCC_Periph) SPI3RST 

func (p *RCC_Periph) SPI3RST() RMAPB1RSTR

func (*RCC_Periph) SRAMEN 

func (p *RCC_Periph) SRAMEN() RMAHBENR

func (*RCC_Periph) SW 

func (p *RCC_Periph) SW() RMCFGR

func (*RCC_Periph) SWS 

func (p *RCC_Periph) SWS() RMCFGR

func (*RCC_Periph) TIM1EN 

func (p *RCC_Periph) TIM1EN() RMAPB2ENR

func (*RCC_Periph) TIM1RST 

func (p *RCC_Periph) TIM1RST() RMAPB2RSTR

func (*RCC_Periph) TIM2EN 

func (p *RCC_Periph) TIM2EN() RMAPB1ENR

func (*RCC_Periph) TIM2RST 

func (p *RCC_Periph) TIM2RST() RMAPB1RSTR

func (*RCC_Periph) TIM3EN 

func (p *RCC_Periph) TIM3EN() RMAPB1ENR

func (*RCC_Periph) TIM3RST 

func (p *RCC_Periph) TIM3RST() RMAPB1RSTR

func (*RCC_Periph) TIM4EN 

func (p *RCC_Periph) TIM4EN() RMAPB1ENR

func (*RCC_Periph) TIM4RST 

func (p *RCC_Periph) TIM4RST() RMAPB1RSTR

func (*RCC_Periph) TIM5EN 

func (p *RCC_Periph) TIM5EN() RMAPB1ENR

func (*RCC_Periph) TIM5RST 

func (p *RCC_Periph) TIM5RST() RMAPB1RSTR

func (*RCC_Periph) TIM6EN 

func (p *RCC_Periph) TIM6EN() RMAPB1ENR

func (*RCC_Periph) TIM6RST 

func (p *RCC_Periph) TIM6RST() RMAPB1RSTR

func (*RCC_Periph) TIM7EN 

func (p *RCC_Periph) TIM7EN() RMAPB1ENR

func (*RCC_Periph) TIM7RST 

func (p *RCC_Periph) TIM7RST() RMAPB1RSTR

func (*RCC_Periph) TIM8EN 

func (p *RCC_Periph) TIM8EN() RMAPB2ENR

func (*RCC_Periph) TIM8RST 

func (p *RCC_Periph) TIM8RST() RMAPB2RSTR

func (*RCC_Periph) UART4EN 

func (p *RCC_Periph) UART4EN() RMAPB1ENR

func (*RCC_Periph) UART4RST 

func (p *RCC_Periph) UART4RST() RMAPB1RSTR

func (*RCC_Periph) UART5EN 

func (p *RCC_Periph) UART5EN() RMAPB1ENR

func (*RCC_Periph) UART5RST 

func (p *RCC_Periph) UART5RST() RMAPB1RSTR

func (*RCC_Periph) USART1EN 

func (p *RCC_Periph) USART1EN() RMAPB2ENR

func (*RCC_Periph) USART1RST 

func (p *RCC_Periph) USART1RST() RMAPB2RSTR

func (*RCC_Periph) USART2EN 

func (p *RCC_Periph) USART2EN() RMAPB1ENR

func (*RCC_Periph) USART2RST 

func (p *RCC_Periph) USART2RST() RMAPB1RSTR

func (*RCC_Periph) USART3EN 

func (p *RCC_Periph) USART3EN() RMAPB1ENR

func (*RCC_Periph) USART3RST 

func (p *RCC_Periph) USART3RST() RMAPB1RSTR

func (*RCC_Periph) USBEN 

func (p *RCC_Periph) USBEN() RMAPB1ENR

func (*RCC_Periph) USBPRE 

func (p *RCC_Periph) USBPRE() RMCFGR

func (*RCC_Periph) USBRST 

func (p *RCC_Periph) USBRST() RMAPB1RSTR

func (*RCC_Periph) WWDGEN 

func (p *RCC_Periph) WWDGEN() RMAPB1ENR

func (*RCC_Periph) WWDGRST 

func (p *RCC_Periph) WWDGRST() RMAPB1RSTR

func (*RCC_Periph) WWDGRSTF 

func (p *RCC_Periph) WWDGRSTF() RMCSR

type RCFGR 

type RCFGR struct{ mmio.U32 }

func (*RCFGR) AtomicClearBits 

func (r *RCFGR) AtomicClearBits(mask CFGR)

func (*RCFGR) AtomicSetBits 

func (r *RCFGR) AtomicSetBits(mask CFGR)

func (*RCFGR) AtomicStoreBits 

func (r *RCFGR) AtomicStoreBits(mask, b CFGR)

func (*RCFGR) Bits 

func (r *RCFGR) Bits(mask CFGR) CFGR

func (*RCFGR) ClearBits 

func (r *RCFGR) ClearBits(mask CFGR)

func (*RCFGR) Load 

func (r *RCFGR) Load() CFGR

func (*RCFGR) SetBits 

func (r *RCFGR) SetBits(mask CFGR)

func (*RCFGR) Store 

func (r *RCFGR) Store(b CFGR)

func (*RCFGR) StoreBits 

func (r *RCFGR) StoreBits(mask, b CFGR)

type RCIR 

type RCIR struct{ mmio.U32 }

func (*RCIR) AtomicClearBits 

func (r *RCIR) AtomicClearBits(mask CIR)

func (*RCIR) AtomicSetBits 

func (r *RCIR) AtomicSetBits(mask CIR)

func (*RCIR) AtomicStoreBits 

func (r *RCIR) AtomicStoreBits(mask, b CIR)

func (*RCIR) Bits 

func (r *RCIR) Bits(mask CIR) CIR

func (*RCIR) ClearBits 

func (r *RCIR) ClearBits(mask CIR)

func (*RCIR) Load 

func (r *RCIR) Load() CIR

func (*RCIR) SetBits 

func (r *RCIR) SetBits(mask CIR)

func (*RCIR) Store 

func (r *RCIR) Store(b CIR)

func (*RCIR) StoreBits 

func (r *RCIR) StoreBits(mask, b CIR)

type RCR 

type RCR struct{ mmio.U32 }

func (*RCR) AtomicClearBits 

func (r *RCR) AtomicClearBits(mask CR)

func (*RCR) AtomicSetBits 

func (r *RCR) AtomicSetBits(mask CR)

func (*RCR) AtomicStoreBits 

func (r *RCR) AtomicStoreBits(mask, b CR)

func (*RCR) Bits 

func (r *RCR) Bits(mask CR) CR

func (*RCR) ClearBits 

func (r *RCR) ClearBits(mask CR)

func (*RCR) Load 

func (r *RCR) Load() CR

func (*RCR) SetBits 

func (r *RCR) SetBits(mask CR)

func (*RCR) Store 

func (r *RCR) Store(b CR)

func (*RCR) StoreBits 

func (r *RCR) StoreBits(mask, b CR)

type RCSR 

type RCSR struct{ mmio.U32 }

func (*RCSR) AtomicClearBits 

func (r *RCSR) AtomicClearBits(mask CSR)

func (*RCSR) AtomicSetBits 

func (r *RCSR) AtomicSetBits(mask CSR)

func (*RCSR) AtomicStoreBits 

func (r *RCSR) AtomicStoreBits(mask, b CSR)

func (*RCSR) Bits 

func (r *RCSR) Bits(mask CSR) CSR

func (*RCSR) ClearBits 

func (r *RCSR) ClearBits(mask CSR)

func (*RCSR) Load 

func (r *RCSR) Load() CSR

func (*RCSR) SetBits 

func (r *RCSR) SetBits(mask CSR)

func (*RCSR) Store 

func (r *RCSR) Store(b CSR)

func (*RCSR) StoreBits 

func (r *RCSR) StoreBits(mask, b CSR)

type RMAHBENR 

type RMAHBENR struct{ mmio.UM32 }

func (RMAHBENR) Load 

func (rm RMAHBENR) Load() AHBENR

func (RMAHBENR) Store 

func (rm RMAHBENR) Store(b AHBENR)

type RMAPB1ENR 

type RMAPB1ENR struct{ mmio.UM32 }

func (RMAPB1ENR) Load 

func (rm RMAPB1ENR) Load() APB1ENR

func (RMAPB1ENR) Store 

func (rm RMAPB1ENR) Store(b APB1ENR)

type RMAPB1RSTR 

type RMAPB1RSTR struct{ mmio.UM32 }

func (RMAPB1RSTR) Load 

func (rm RMAPB1RSTR) Load() APB1RSTR

func (RMAPB1RSTR) Store 

func (rm RMAPB1RSTR) Store(b APB1RSTR)

type RMAPB2ENR 

type RMAPB2ENR struct{ mmio.UM32 }

func (RMAPB2ENR) Load 

func (rm RMAPB2ENR) Load() APB2ENR

func (RMAPB2ENR) Store 

func (rm RMAPB2ENR) Store(b APB2ENR)

type RMAPB2RSTR 

type RMAPB2RSTR struct{ mmio.UM32 }

func (RMAPB2RSTR) Load 

func (rm RMAPB2RSTR) Load() APB2RSTR

func (RMAPB2RSTR) Store 

func (rm RMAPB2RSTR) Store(b APB2RSTR)

type RMBDCR 

type RMBDCR struct{ mmio.UM32 }

func (RMBDCR) Load 

func (rm RMBDCR) Load() BDCR

func (RMBDCR) Store 

func (rm RMBDCR) Store(b BDCR)

type RMCFGR 

type RMCFGR struct{ mmio.UM32 }

func (RMCFGR) Load 

func (rm RMCFGR) Load() CFGR

func (RMCFGR) Store 

func (rm RMCFGR) Store(b CFGR)

type RMCIR 

type RMCIR struct{ mmio.UM32 }

func (RMCIR) Load 

func (rm RMCIR) Load() CIR

func (RMCIR) Store 

func (rm RMCIR) Store(b CIR)

type RMCR 

type RMCR struct{ mmio.UM32 }

func (RMCR) Load 

func (rm RMCR) Load() CR

func (RMCR) Store 

func (rm RMCR) Store(b CR)

type RMCSR 

type RMCSR struct{ mmio.UM32 }

func (RMCSR) Load 

func (rm RMCSR) Load() CSR

func (RMCSR) Store 

func (rm RMCSR) Store(b CSR)

Source Files

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