tsc

package
v0.0.0-...-3d984ba Latest Latest
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 Go to latest Published: Nov 29, 2018 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package tsc provides interface to Touch Sensing Controller (TSC).

Peripheral: TSC_Periph Touch Sensing Controller (TSC). Instances: 

TSC  mmap.TSC_BASE

Registers: 

0x00 32  CR        Control register.
0x04 32  IER       Interrupt enable register.
0x08 32  ICR       Interrupt clear register.
0x0C 32  ISR       Interrupt status register.
0x10 32  IOHCR     I/O hysteresis control register.
0x18 32  IOASCR    I/O analog switch control register.
0x20 32  IOSCR     I/O sampling control register.
0x28 32  IOCCR     I/O channel control register.
0x30 32  IOGCSR    I/O group control status register.
0x34 32  IOGXCR[8] I/O group x counter register.

Import: 

stm32/o/f303xe/mmap

Index

Constants

View Source 
const (
	TSCEn    = 0
	STARTn   = 1
	AMn      = 2
	SYNCPOLn = 3
	IODEFn   = 4
	MCVn     = 5
	PGPSCn   = 12
	SSPSCn   = 15
	SSEn     = 16
	SSDn     = 17
	CTPLn    = 24
	CTPHn    = 28
)
View Source 
const (
	EOAIEn = 0
	MCEIEn = 1
)
View Source 
const (
	EOAICn = 0
	MCEICn = 1
)
View Source 
const (
	EOAFn = 0
	MCEFn = 1
)
View Source 
const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)
View Source 
const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)
View Source 
const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)
View Source 
const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)
View Source 
const (
	G1En = 0
	G2En = 1
	G3En = 2
	G4En = 3
	G5En = 4
	G6En = 5
	G7En = 6
	G8En = 7
	G1Sn = 16
	G2Sn = 17
	G3Sn = 18
	G4Sn = 19
	G5Sn = 20
	G6Sn = 21
	G7Sn = 22
	G8Sn = 23
)
View Source 
const (
	CNTn = 0
)

Variables

View Source 
var TSC = (*TSC_Periph)(unsafe.Pointer(uintptr(mmap.TSC_BASE)))

Functions

This section is empty.

Types

type CR 

type CR uint32
const (
	TSCE    CR = 0x01 << 0  //+ Touch sensing controller enable.
	START   CR = 0x01 << 1  //+ Start acquisition.
	AM      CR = 0x01 << 2  //+ Acquisition mode.
	SYNCPOL CR = 0x01 << 3  //+ Synchronization pin polarity.
	IODEF   CR = 0x01 << 4  //+ IO default mode.
	MCV     CR = 0x07 << 5  //+ MCV[2:0] bits (Max Count Value).
	PGPSC   CR = 0x07 << 12 //+ PGPSC[2:0] bits (Pulse Generator Prescaler).
	SSPSC   CR = 0x01 << 15 //+ Spread Spectrum Prescaler.
	SSE     CR = 0x01 << 16 //+ Spread Spectrum Enable.
	SSD     CR = 0x7F << 17 //+ SSD[6:0] bits (Spread Spectrum Deviation).
	CTPL    CR = 0x0F << 24 //+ CTPL[3:0] bits (Charge Transfer pulse low).
	CTPH    CR = 0x0F << 28 //+ CTPH[3:0] bits (Charge Transfer pulse high).
)

func (CR) Field 

func (b CR) Field(mask CR) int

func (CR) J 

func (mask CR) J(v int) CR

type ICR 

type ICR uint32
const (
	EOAIC ICR = 0x01 << 0 //+ End of acquisition interrupt clear.
	MCEIC ICR = 0x01 << 1 //+ Max count error interrupt clear.
)

func (ICR) Field 

func (b ICR) Field(mask ICR) int

func (ICR) J 

func (mask ICR) J(v int) ICR

type IER 

type IER uint32
const (
	EOAIE IER = 0x01 << 0 //+ End of acquisition interrupt enable.
	MCEIE IER = 0x01 << 1 //+ Max count error interrupt enable.
)

func (IER) Field 

func (b IER) Field(mask IER) int

func (IER) J 

func (mask IER) J(v int) IER

type IOASCR 

type IOASCR uint32
const (
	G1_IO1 IOASCR = 0x01 << 0  //+ GROUP1_IO1 analog switch enable.
	G1_IO2 IOASCR = 0x01 << 1  //+ GROUP1_IO2 analog switch enable.
	G1_IO3 IOASCR = 0x01 << 2  //+ GROUP1_IO3 analog switch enable.
	G1_IO4 IOASCR = 0x01 << 3  //+ GROUP1_IO4 analog switch enable.
	G2_IO1 IOASCR = 0x01 << 4  //+ GROUP2_IO1 analog switch enable.
	G2_IO2 IOASCR = 0x01 << 5  //+ GROUP2_IO2 analog switch enable.
	G2_IO3 IOASCR = 0x01 << 6  //+ GROUP2_IO3 analog switch enable.
	G2_IO4 IOASCR = 0x01 << 7  //+ GROUP2_IO4 analog switch enable.
	G3_IO1 IOASCR = 0x01 << 8  //+ GROUP3_IO1 analog switch enable.
	G3_IO2 IOASCR = 0x01 << 9  //+ GROUP3_IO2 analog switch enable.
	G3_IO3 IOASCR = 0x01 << 10 //+ GROUP3_IO3 analog switch enable.
	G3_IO4 IOASCR = 0x01 << 11 //+ GROUP3_IO4 analog switch enable.
	G4_IO1 IOASCR = 0x01 << 12 //+ GROUP4_IO1 analog switch enable.
	G4_IO2 IOASCR = 0x01 << 13 //+ GROUP4_IO2 analog switch enable.
	G4_IO3 IOASCR = 0x01 << 14 //+ GROUP4_IO3 analog switch enable.
	G4_IO4 IOASCR = 0x01 << 15 //+ GROUP4_IO4 analog switch enable.
	G5_IO1 IOASCR = 0x01 << 16 //+ GROUP5_IO1 analog switch enable.
	G5_IO2 IOASCR = 0x01 << 17 //+ GROUP5_IO2 analog switch enable.
	G5_IO3 IOASCR = 0x01 << 18 //+ GROUP5_IO3 analog switch enable.
	G5_IO4 IOASCR = 0x01 << 19 //+ GROUP5_IO4 analog switch enable.
	G6_IO1 IOASCR = 0x01 << 20 //+ GROUP6_IO1 analog switch enable.
	G6_IO2 IOASCR = 0x01 << 21 //+ GROUP6_IO2 analog switch enable.
	G6_IO3 IOASCR = 0x01 << 22 //+ GROUP6_IO3 analog switch enable.
	G6_IO4 IOASCR = 0x01 << 23 //+ GROUP6_IO4 analog switch enable.
	G7_IO1 IOASCR = 0x01 << 24 //+ GROUP7_IO1 analog switch enable.
	G7_IO2 IOASCR = 0x01 << 25 //+ GROUP7_IO2 analog switch enable.
	G7_IO3 IOASCR = 0x01 << 26 //+ GROUP7_IO3 analog switch enable.
	G7_IO4 IOASCR = 0x01 << 27 //+ GROUP7_IO4 analog switch enable.
	G8_IO1 IOASCR = 0x01 << 28 //+ GROUP8_IO1 analog switch enable.
	G8_IO2 IOASCR = 0x01 << 29 //+ GROUP8_IO2 analog switch enable.
	G8_IO3 IOASCR = 0x01 << 30 //+ GROUP8_IO3 analog switch enable.
	G8_IO4 IOASCR = 0x01 << 31 //+ GROUP8_IO4 analog switch enable.
)

func (IOASCR) Field 

func (b IOASCR) Field(mask IOASCR) int

func (IOASCR) J 

func (mask IOASCR) J(v int) IOASCR

type IOCCR 

type IOCCR uint32
const (
	G1_IO1 IOCCR = 0x01 << 0  //+ GROUP1_IO1 channel mode.
	G1_IO2 IOCCR = 0x01 << 1  //+ GROUP1_IO2 channel mode.
	G1_IO3 IOCCR = 0x01 << 2  //+ GROUP1_IO3 channel mode.
	G1_IO4 IOCCR = 0x01 << 3  //+ GROUP1_IO4 channel mode.
	G2_IO1 IOCCR = 0x01 << 4  //+ GROUP2_IO1 channel mode.
	G2_IO2 IOCCR = 0x01 << 5  //+ GROUP2_IO2 channel mode.
	G2_IO3 IOCCR = 0x01 << 6  //+ GROUP2_IO3 channel mode.
	G2_IO4 IOCCR = 0x01 << 7  //+ GROUP2_IO4 channel mode.
	G3_IO1 IOCCR = 0x01 << 8  //+ GROUP3_IO1 channel mode.
	G3_IO2 IOCCR = 0x01 << 9  //+ GROUP3_IO2 channel mode.
	G3_IO3 IOCCR = 0x01 << 10 //+ GROUP3_IO3 channel mode.
	G3_IO4 IOCCR = 0x01 << 11 //+ GROUP3_IO4 channel mode.
	G4_IO1 IOCCR = 0x01 << 12 //+ GROUP4_IO1 channel mode.
	G4_IO2 IOCCR = 0x01 << 13 //+ GROUP4_IO2 channel mode.
	G4_IO3 IOCCR = 0x01 << 14 //+ GROUP4_IO3 channel mode.
	G4_IO4 IOCCR = 0x01 << 15 //+ GROUP4_IO4 channel mode.
	G5_IO1 IOCCR = 0x01 << 16 //+ GROUP5_IO1 channel mode.
	G5_IO2 IOCCR = 0x01 << 17 //+ GROUP5_IO2 channel mode.
	G5_IO3 IOCCR = 0x01 << 18 //+ GROUP5_IO3 channel mode.
	G5_IO4 IOCCR = 0x01 << 19 //+ GROUP5_IO4 channel mode.
	G6_IO1 IOCCR = 0x01 << 20 //+ GROUP6_IO1 channel mode.
	G6_IO2 IOCCR = 0x01 << 21 //+ GROUP6_IO2 channel mode.
	G6_IO3 IOCCR = 0x01 << 22 //+ GROUP6_IO3 channel mode.
	G6_IO4 IOCCR = 0x01 << 23 //+ GROUP6_IO4 channel mode.
	G7_IO1 IOCCR = 0x01 << 24 //+ GROUP7_IO1 channel mode.
	G7_IO2 IOCCR = 0x01 << 25 //+ GROUP7_IO2 channel mode.
	G7_IO3 IOCCR = 0x01 << 26 //+ GROUP7_IO3 channel mode.
	G7_IO4 IOCCR = 0x01 << 27 //+ GROUP7_IO4 channel mode.
	G8_IO1 IOCCR = 0x01 << 28 //+ GROUP8_IO1 channel mode.
	G8_IO2 IOCCR = 0x01 << 29 //+ GROUP8_IO2 channel mode.
	G8_IO3 IOCCR = 0x01 << 30 //+ GROUP8_IO3 channel mode.
	G8_IO4 IOCCR = 0x01 << 31 //+ GROUP8_IO4 channel mode.
)

func (IOCCR) Field 

func (b IOCCR) Field(mask IOCCR) int

func (IOCCR) J 

func (mask IOCCR) J(v int) IOCCR

type IOGCSR 

type IOGCSR uint32
const (
	G1E IOGCSR = 0x01 << 0  //+ Analog IO GROUP1 enable.
	G2E IOGCSR = 0x01 << 1  //+ Analog IO GROUP2 enable.
	G3E IOGCSR = 0x01 << 2  //+ Analog IO GROUP3 enable.
	G4E IOGCSR = 0x01 << 3  //+ Analog IO GROUP4 enable.
	G5E IOGCSR = 0x01 << 4  //+ Analog IO GROUP5 enable.
	G6E IOGCSR = 0x01 << 5  //+ Analog IO GROUP6 enable.
	G7E IOGCSR = 0x01 << 6  //+ Analog IO GROUP7 enable.
	G8E IOGCSR = 0x01 << 7  //+ Analog IO GROUP8 enable.
	G1S IOGCSR = 0x01 << 16 //+ Analog IO GROUP1 status.
	G2S IOGCSR = 0x01 << 17 //+ Analog IO GROUP2 status.
	G3S IOGCSR = 0x01 << 18 //+ Analog IO GROUP3 status.
	G4S IOGCSR = 0x01 << 19 //+ Analog IO GROUP4 status.
	G5S IOGCSR = 0x01 << 20 //+ Analog IO GROUP5 status.
	G6S IOGCSR = 0x01 << 21 //+ Analog IO GROUP6 status.
	G7S IOGCSR = 0x01 << 22 //+ Analog IO GROUP7 status.
	G8S IOGCSR = 0x01 << 23 //+ Analog IO GROUP8 status.
)

func (IOGCSR) Field 

func (b IOGCSR) Field(mask IOGCSR) int

func (IOGCSR) J 

func (mask IOGCSR) J(v int) IOGCSR

type IOGXCR 

type IOGXCR uint32
const (
	CNT IOGXCR = 0x3FFF << 0 //+ CNT[13:0] bits (Counter value).
)

func (IOGXCR) Field 

func (b IOGXCR) Field(mask IOGXCR) int

func (IOGXCR) J 

func (mask IOGXCR) J(v int) IOGXCR

type IOHCR 

type IOHCR uint32
const (
	G1_IO1 IOHCR = 0x01 << 0  //+ GROUP1_IO1 schmitt trigger hysteresis mode.
	G1_IO2 IOHCR = 0x01 << 1  //+ GROUP1_IO2 schmitt trigger hysteresis mode.
	G1_IO3 IOHCR = 0x01 << 2  //+ GROUP1_IO3 schmitt trigger hysteresis mode.
	G1_IO4 IOHCR = 0x01 << 3  //+ GROUP1_IO4 schmitt trigger hysteresis mode.
	G2_IO1 IOHCR = 0x01 << 4  //+ GROUP2_IO1 schmitt trigger hysteresis mode.
	G2_IO2 IOHCR = 0x01 << 5  //+ GROUP2_IO2 schmitt trigger hysteresis mode.
	G2_IO3 IOHCR = 0x01 << 6  //+ GROUP2_IO3 schmitt trigger hysteresis mode.
	G2_IO4 IOHCR = 0x01 << 7  //+ GROUP2_IO4 schmitt trigger hysteresis mode.
	G3_IO1 IOHCR = 0x01 << 8  //+ GROUP3_IO1 schmitt trigger hysteresis mode.
	G3_IO2 IOHCR = 0x01 << 9  //+ GROUP3_IO2 schmitt trigger hysteresis mode.
	G3_IO3 IOHCR = 0x01 << 10 //+ GROUP3_IO3 schmitt trigger hysteresis mode.
	G3_IO4 IOHCR = 0x01 << 11 //+ GROUP3_IO4 schmitt trigger hysteresis mode.
	G4_IO1 IOHCR = 0x01 << 12 //+ GROUP4_IO1 schmitt trigger hysteresis mode.
	G4_IO2 IOHCR = 0x01 << 13 //+ GROUP4_IO2 schmitt trigger hysteresis mode.
	G4_IO3 IOHCR = 0x01 << 14 //+ GROUP4_IO3 schmitt trigger hysteresis mode.
	G4_IO4 IOHCR = 0x01 << 15 //+ GROUP4_IO4 schmitt trigger hysteresis mode.
	G5_IO1 IOHCR = 0x01 << 16 //+ GROUP5_IO1 schmitt trigger hysteresis mode.
	G5_IO2 IOHCR = 0x01 << 17 //+ GROUP5_IO2 schmitt trigger hysteresis mode.
	G5_IO3 IOHCR = 0x01 << 18 //+ GROUP5_IO3 schmitt trigger hysteresis mode.
	G5_IO4 IOHCR = 0x01 << 19 //+ GROUP5_IO4 schmitt trigger hysteresis mode.
	G6_IO1 IOHCR = 0x01 << 20 //+ GROUP6_IO1 schmitt trigger hysteresis mode.
	G6_IO2 IOHCR = 0x01 << 21 //+ GROUP6_IO2 schmitt trigger hysteresis mode.
	G6_IO3 IOHCR = 0x01 << 22 //+ GROUP6_IO3 schmitt trigger hysteresis mode.
	G6_IO4 IOHCR = 0x01 << 23 //+ GROUP6_IO4 schmitt trigger hysteresis mode.
	G7_IO1 IOHCR = 0x01 << 24 //+ GROUP7_IO1 schmitt trigger hysteresis mode.
	G7_IO2 IOHCR = 0x01 << 25 //+ GROUP7_IO2 schmitt trigger hysteresis mode.
	G7_IO3 IOHCR = 0x01 << 26 //+ GROUP7_IO3 schmitt trigger hysteresis mode.
	G7_IO4 IOHCR = 0x01 << 27 //+ GROUP7_IO4 schmitt trigger hysteresis mode.
	G8_IO1 IOHCR = 0x01 << 28 //+ GROUP8_IO1 schmitt trigger hysteresis mode.
	G8_IO2 IOHCR = 0x01 << 29 //+ GROUP8_IO2 schmitt trigger hysteresis mode.
	G8_IO3 IOHCR = 0x01 << 30 //+ GROUP8_IO3 schmitt trigger hysteresis mode.
	G8_IO4 IOHCR = 0x01 << 31 //+ GROUP8_IO4 schmitt trigger hysteresis mode.
)

func (IOHCR) Field 

func (b IOHCR) Field(mask IOHCR) int

func (IOHCR) J 

func (mask IOHCR) J(v int) IOHCR

type IOSCR 

type IOSCR uint32
const (
	G1_IO1 IOSCR = 0x01 << 0  //+ GROUP1_IO1 sampling mode.
	G1_IO2 IOSCR = 0x01 << 1  //+ GROUP1_IO2 sampling mode.
	G1_IO3 IOSCR = 0x01 << 2  //+ GROUP1_IO3 sampling mode.
	G1_IO4 IOSCR = 0x01 << 3  //+ GROUP1_IO4 sampling mode.
	G2_IO1 IOSCR = 0x01 << 4  //+ GROUP2_IO1 sampling mode.
	G2_IO2 IOSCR = 0x01 << 5  //+ GROUP2_IO2 sampling mode.
	G2_IO3 IOSCR = 0x01 << 6  //+ GROUP2_IO3 sampling mode.
	G2_IO4 IOSCR = 0x01 << 7  //+ GROUP2_IO4 sampling mode.
	G3_IO1 IOSCR = 0x01 << 8  //+ GROUP3_IO1 sampling mode.
	G3_IO2 IOSCR = 0x01 << 9  //+ GROUP3_IO2 sampling mode.
	G3_IO3 IOSCR = 0x01 << 10 //+ GROUP3_IO3 sampling mode.
	G3_IO4 IOSCR = 0x01 << 11 //+ GROUP3_IO4 sampling mode.
	G4_IO1 IOSCR = 0x01 << 12 //+ GROUP4_IO1 sampling mode.
	G4_IO2 IOSCR = 0x01 << 13 //+ GROUP4_IO2 sampling mode.
	G4_IO3 IOSCR = 0x01 << 14 //+ GROUP4_IO3 sampling mode.
	G4_IO4 IOSCR = 0x01 << 15 //+ GROUP4_IO4 sampling mode.
	G5_IO1 IOSCR = 0x01 << 16 //+ GROUP5_IO1 sampling mode.
	G5_IO2 IOSCR = 0x01 << 17 //+ GROUP5_IO2 sampling mode.
	G5_IO3 IOSCR = 0x01 << 18 //+ GROUP5_IO3 sampling mode.
	G5_IO4 IOSCR = 0x01 << 19 //+ GROUP5_IO4 sampling mode.
	G6_IO1 IOSCR = 0x01 << 20 //+ GROUP6_IO1 sampling mode.
	G6_IO2 IOSCR = 0x01 << 21 //+ GROUP6_IO2 sampling mode.
	G6_IO3 IOSCR = 0x01 << 22 //+ GROUP6_IO3 sampling mode.
	G6_IO4 IOSCR = 0x01 << 23 //+ GROUP6_IO4 sampling mode.
	G7_IO1 IOSCR = 0x01 << 24 //+ GROUP7_IO1 sampling mode.
	G7_IO2 IOSCR = 0x01 << 25 //+ GROUP7_IO2 sampling mode.
	G7_IO3 IOSCR = 0x01 << 26 //+ GROUP7_IO3 sampling mode.
	G7_IO4 IOSCR = 0x01 << 27 //+ GROUP7_IO4 sampling mode.
	G8_IO1 IOSCR = 0x01 << 28 //+ GROUP8_IO1 sampling mode.
	G8_IO2 IOSCR = 0x01 << 29 //+ GROUP8_IO2 sampling mode.
	G8_IO3 IOSCR = 0x01 << 30 //+ GROUP8_IO3 sampling mode.
	G8_IO4 IOSCR = 0x01 << 31 //+ GROUP8_IO4 sampling mode.
)

func (IOSCR) Field 

func (b IOSCR) Field(mask IOSCR) int

func (IOSCR) J 

func (mask IOSCR) J(v int) IOSCR

type ISR 

type ISR uint32
const (
	EOAF ISR = 0x01 << 0 //+ End of acquisition flag.
	MCEF ISR = 0x01 << 1 //+ Max count error flag.
)

func (ISR) Field 

func (b ISR) Field(mask ISR) int

func (ISR) J 

func (mask ISR) J(v int) ISR

type RCR 

type RCR struct{ mmio.U32 }

func (*RCR) AtomicClearBits 

func (r *RCR) AtomicClearBits(mask CR)

func (*RCR) AtomicSetBits 

func (r *RCR) AtomicSetBits(mask CR)

func (*RCR) AtomicStoreBits 

func (r *RCR) AtomicStoreBits(mask, b CR)

func (*RCR) Bits 

func (r *RCR) Bits(mask CR) CR

func (*RCR) ClearBits 

func (r *RCR) ClearBits(mask CR)

func (*RCR) Load 

func (r *RCR) Load() CR

func (*RCR) SetBits 

func (r *RCR) SetBits(mask CR)

func (*RCR) Store 

func (r *RCR) Store(b CR)

func (*RCR) StoreBits 

func (r *RCR) StoreBits(mask, b CR)

type RICR 

type RICR struct{ mmio.U32 }

func (*RICR) AtomicClearBits 

func (r *RICR) AtomicClearBits(mask ICR)

func (*RICR) AtomicSetBits 

func (r *RICR) AtomicSetBits(mask ICR)

func (*RICR) AtomicStoreBits 

func (r *RICR) AtomicStoreBits(mask, b ICR)

func (*RICR) Bits 

func (r *RICR) Bits(mask ICR) ICR

func (*RICR) ClearBits 

func (r *RICR) ClearBits(mask ICR)

func (*RICR) Load 

func (r *RICR) Load() ICR

func (*RICR) SetBits 

func (r *RICR) SetBits(mask ICR)

func (*RICR) Store 

func (r *RICR) Store(b ICR)

func (*RICR) StoreBits 

func (r *RICR) StoreBits(mask, b ICR)

type RIER 

type RIER struct{ mmio.U32 }

func (*RIER) AtomicClearBits 

func (r *RIER) AtomicClearBits(mask IER)

func (*RIER) AtomicSetBits 

func (r *RIER) AtomicSetBits(mask IER)

func (*RIER) AtomicStoreBits 

func (r *RIER) AtomicStoreBits(mask, b IER)

func (*RIER) Bits 

func (r *RIER) Bits(mask IER) IER

func (*RIER) ClearBits 

func (r *RIER) ClearBits(mask IER)

func (*RIER) Load 

func (r *RIER) Load() IER

func (*RIER) SetBits 

func (r *RIER) SetBits(mask IER)

func (*RIER) Store 

func (r *RIER) Store(b IER)

func (*RIER) StoreBits 

func (r *RIER) StoreBits(mask, b IER)

type RIOASCR 

type RIOASCR struct{ mmio.U32 }

func (*RIOASCR) AtomicClearBits 

func (r *RIOASCR) AtomicClearBits(mask IOASCR)

func (*RIOASCR) AtomicSetBits 

func (r *RIOASCR) AtomicSetBits(mask IOASCR)

func (*RIOASCR) AtomicStoreBits 

func (r *RIOASCR) AtomicStoreBits(mask, b IOASCR)

func (*RIOASCR) Bits 

func (r *RIOASCR) Bits(mask IOASCR) IOASCR

func (*RIOASCR) ClearBits 

func (r *RIOASCR) ClearBits(mask IOASCR)

func (*RIOASCR) Load 

func (r *RIOASCR) Load() IOASCR

func (*RIOASCR) SetBits 

func (r *RIOASCR) SetBits(mask IOASCR)

func (*RIOASCR) Store 

func (r *RIOASCR) Store(b IOASCR)

func (*RIOASCR) StoreBits 

func (r *RIOASCR) StoreBits(mask, b IOASCR)

type RIOCCR 

type RIOCCR struct{ mmio.U32 }

func (*RIOCCR) AtomicClearBits 

func (r *RIOCCR) AtomicClearBits(mask IOCCR)

func (*RIOCCR) AtomicSetBits 

func (r *RIOCCR) AtomicSetBits(mask IOCCR)

func (*RIOCCR) AtomicStoreBits 

func (r *RIOCCR) AtomicStoreBits(mask, b IOCCR)

func (*RIOCCR) Bits 

func (r *RIOCCR) Bits(mask IOCCR) IOCCR

func (*RIOCCR) ClearBits 

func (r *RIOCCR) ClearBits(mask IOCCR)

func (*RIOCCR) Load 

func (r *RIOCCR) Load() IOCCR

func (*RIOCCR) SetBits 

func (r *RIOCCR) SetBits(mask IOCCR)

func (*RIOCCR) Store 

func (r *RIOCCR) Store(b IOCCR)

func (*RIOCCR) StoreBits 

func (r *RIOCCR) StoreBits(mask, b IOCCR)

type RIOGCSR 

type RIOGCSR struct{ mmio.U32 }

func (*RIOGCSR) AtomicClearBits 

func (r *RIOGCSR) AtomicClearBits(mask IOGCSR)

func (*RIOGCSR) AtomicSetBits 

func (r *RIOGCSR) AtomicSetBits(mask IOGCSR)

func (*RIOGCSR) AtomicStoreBits 

func (r *RIOGCSR) AtomicStoreBits(mask, b IOGCSR)

func (*RIOGCSR) Bits 

func (r *RIOGCSR) Bits(mask IOGCSR) IOGCSR

func (*RIOGCSR) ClearBits 

func (r *RIOGCSR) ClearBits(mask IOGCSR)

func (*RIOGCSR) Load 

func (r *RIOGCSR) Load() IOGCSR

func (*RIOGCSR) SetBits 

func (r *RIOGCSR) SetBits(mask IOGCSR)

func (*RIOGCSR) Store 

func (r *RIOGCSR) Store(b IOGCSR)

func (*RIOGCSR) StoreBits 

func (r *RIOGCSR) StoreBits(mask, b IOGCSR)

type RIOGXCR 

type RIOGXCR struct{ mmio.U32 }

func (*RIOGXCR) AtomicClearBits 

func (r *RIOGXCR) AtomicClearBits(mask IOGXCR)

func (*RIOGXCR) AtomicSetBits 

func (r *RIOGXCR) AtomicSetBits(mask IOGXCR)

func (*RIOGXCR) AtomicStoreBits 

func (r *RIOGXCR) AtomicStoreBits(mask, b IOGXCR)

func (*RIOGXCR) Bits 

func (r *RIOGXCR) Bits(mask IOGXCR) IOGXCR

func (*RIOGXCR) ClearBits 

func (r *RIOGXCR) ClearBits(mask IOGXCR)

func (*RIOGXCR) Load 

func (r *RIOGXCR) Load() IOGXCR

func (*RIOGXCR) SetBits 

func (r *RIOGXCR) SetBits(mask IOGXCR)

func (*RIOGXCR) Store 

func (r *RIOGXCR) Store(b IOGXCR)

func (*RIOGXCR) StoreBits 

func (r *RIOGXCR) StoreBits(mask, b IOGXCR)

type RIOHCR 

type RIOHCR struct{ mmio.U32 }

func (*RIOHCR) AtomicClearBits 

func (r *RIOHCR) AtomicClearBits(mask IOHCR)

func (*RIOHCR) AtomicSetBits 

func (r *RIOHCR) AtomicSetBits(mask IOHCR)

func (*RIOHCR) AtomicStoreBits 

func (r *RIOHCR) AtomicStoreBits(mask, b IOHCR)

func (*RIOHCR) Bits 

func (r *RIOHCR) Bits(mask IOHCR) IOHCR

func (*RIOHCR) ClearBits 

func (r *RIOHCR) ClearBits(mask IOHCR)

func (*RIOHCR) Load 

func (r *RIOHCR) Load() IOHCR

func (*RIOHCR) SetBits 

func (r *RIOHCR) SetBits(mask IOHCR)

func (*RIOHCR) Store 

func (r *RIOHCR) Store(b IOHCR)

func (*RIOHCR) StoreBits 

func (r *RIOHCR) StoreBits(mask, b IOHCR)

type RIOSCR 

type RIOSCR struct{ mmio.U32 }

func (*RIOSCR) AtomicClearBits 

func (r *RIOSCR) AtomicClearBits(mask IOSCR)

func (*RIOSCR) AtomicSetBits 

func (r *RIOSCR) AtomicSetBits(mask IOSCR)

func (*RIOSCR) AtomicStoreBits 

func (r *RIOSCR) AtomicStoreBits(mask, b IOSCR)

func (*RIOSCR) Bits 

func (r *RIOSCR) Bits(mask IOSCR) IOSCR

func (*RIOSCR) ClearBits 

func (r *RIOSCR) ClearBits(mask IOSCR)

func (*RIOSCR) Load 

func (r *RIOSCR) Load() IOSCR

func (*RIOSCR) SetBits 

func (r *RIOSCR) SetBits(mask IOSCR)

func (*RIOSCR) Store 

func (r *RIOSCR) Store(b IOSCR)

func (*RIOSCR) StoreBits 

func (r *RIOSCR) StoreBits(mask, b IOSCR)

type RISR 

type RISR struct{ mmio.U32 }

func (*RISR) AtomicClearBits 

func (r *RISR) AtomicClearBits(mask ISR)

func (*RISR) AtomicSetBits 

func (r *RISR) AtomicSetBits(mask ISR)

func (*RISR) AtomicStoreBits 

func (r *RISR) AtomicStoreBits(mask, b ISR)

func (*RISR) Bits 

func (r *RISR) Bits(mask ISR) ISR

func (*RISR) ClearBits 

func (r *RISR) ClearBits(mask ISR)

func (*RISR) Load 

func (r *RISR) Load() ISR

func (*RISR) SetBits 

func (r *RISR) SetBits(mask ISR)

func (*RISR) Store 

func (r *RISR) Store(b ISR)

func (*RISR) StoreBits 

func (r *RISR) StoreBits(mask, b ISR)

type RMCR 

type RMCR struct{ mmio.UM32 }

func (RMCR) Load 

func (rm RMCR) Load() CR

func (RMCR) Store 

func (rm RMCR) Store(b CR)

type RMICR 

type RMICR struct{ mmio.UM32 }

func (RMICR) Load 

func (rm RMICR) Load() ICR

func (RMICR) Store 

func (rm RMICR) Store(b ICR)

type RMIER 

type RMIER struct{ mmio.UM32 }

func (RMIER) Load 

func (rm RMIER) Load() IER

func (RMIER) Store 

func (rm RMIER) Store(b IER)

type RMIOASCR 

type RMIOASCR struct{ mmio.UM32 }

func (RMIOASCR) Load 

func (rm RMIOASCR) Load() IOASCR

func (RMIOASCR) Store 

func (rm RMIOASCR) Store(b IOASCR)

type RMIOCCR 

type RMIOCCR struct{ mmio.UM32 }

func (RMIOCCR) Load 

func (rm RMIOCCR) Load() IOCCR

func (RMIOCCR) Store 

func (rm RMIOCCR) Store(b IOCCR)

type RMIOGCSR 

type RMIOGCSR struct{ mmio.UM32 }

func (RMIOGCSR) Load 

func (rm RMIOGCSR) Load() IOGCSR

func (RMIOGCSR) Store 

func (rm RMIOGCSR) Store(b IOGCSR)

type RMIOGXCR 

type RMIOGXCR struct{ mmio.UM32 }

func (RMIOGXCR) Load 

func (rm RMIOGXCR) Load() IOGXCR

func (RMIOGXCR) Store 

func (rm RMIOGXCR) Store(b IOGXCR)

type RMIOHCR 

type RMIOHCR struct{ mmio.UM32 }

func (RMIOHCR) Load 

func (rm RMIOHCR) Load() IOHCR

func (RMIOHCR) Store 

func (rm RMIOHCR) Store(b IOHCR)

type RMIOSCR 

type RMIOSCR struct{ mmio.UM32 }

func (RMIOSCR) Load 

func (rm RMIOSCR) Load() IOSCR

func (RMIOSCR) Store 

func (rm RMIOSCR) Store(b IOSCR)

type RMISR 

type RMISR struct{ mmio.UM32 }

func (RMISR) Load 

func (rm RMISR) Load() ISR

func (RMISR) Store 

func (rm RMISR) Store(b ISR)

type TSC_Periph 

type TSC_Periph struct {
	CR    RCR
	IER   RIER
	ICR   RICR
	ISR   RISR
	IOHCR RIOHCR

	IOASCR RIOASCR

	IOSCR RIOSCR

	IOCCR RIOCCR

	IOGCSR RIOGCSR
	IOGXCR [8]RIOGXCR
	// contains filtered or unexported fields
}

func (*TSC_Periph) AM 

func (p *TSC_Periph) AM() RMCR

func (*TSC_Periph) BaseAddr 

func (p *TSC_Periph) BaseAddr() uintptr

func (*TSC_Periph) CNT 

func (p *TSC_Periph) CNT(n int) RMIOGXCR

func (*TSC_Periph) CTPH 

func (p *TSC_Periph) CTPH() RMCR

func (*TSC_Periph) CTPL 

func (p *TSC_Periph) CTPL() RMCR

func (*TSC_Periph) EOAF 

func (p *TSC_Periph) EOAF() RMISR

func (*TSC_Periph) EOAIC 

func (p *TSC_Periph) EOAIC() RMICR

func (*TSC_Periph) EOAIE 

func (p *TSC_Periph) EOAIE() RMIER

func (*TSC_Periph) G1E 

func (p *TSC_Periph) G1E() RMIOGCSR

func (*TSC_Periph) G1S 

func (p *TSC_Periph) G1S() RMIOGCSR

func (*TSC_Periph) G1_IO1 

func (p *TSC_Periph) G1_IO1() RMIOCCR

func (*TSC_Periph) G1_IO2 

func (p *TSC_Periph) G1_IO2() RMIOCCR

func (*TSC_Periph) G1_IO3 

func (p *TSC_Periph) G1_IO3() RMIOCCR

func (*TSC_Periph) G1_IO4 

func (p *TSC_Periph) G1_IO4() RMIOCCR

func (*TSC_Periph) G2E 

func (p *TSC_Periph) G2E() RMIOGCSR

func (*TSC_Periph) G2S 

func (p *TSC_Periph) G2S() RMIOGCSR

func (*TSC_Periph) G2_IO1 

func (p *TSC_Periph) G2_IO1() RMIOCCR

func (*TSC_Periph) G2_IO2 

func (p *TSC_Periph) G2_IO2() RMIOCCR

func (*TSC_Periph) G2_IO3 

func (p *TSC_Periph) G2_IO3() RMIOCCR

func (*TSC_Periph) G2_IO4 

func (p *TSC_Periph) G2_IO4() RMIOCCR

func (*TSC_Periph) G3E 

func (p *TSC_Periph) G3E() RMIOGCSR

func (*TSC_Periph) G3S 

func (p *TSC_Periph) G3S() RMIOGCSR

func (*TSC_Periph) G3_IO1 

func (p *TSC_Periph) G3_IO1() RMIOCCR

func (*TSC_Periph) G3_IO2 

func (p *TSC_Periph) G3_IO2() RMIOCCR

func (*TSC_Periph) G3_IO3 

func (p *TSC_Periph) G3_IO3() RMIOCCR

func (*TSC_Periph) G3_IO4 

func (p *TSC_Periph) G3_IO4() RMIOCCR

func (*TSC_Periph) G4E 

func (p *TSC_Periph) G4E() RMIOGCSR

func (*TSC_Periph) G4S 

func (p *TSC_Periph) G4S() RMIOGCSR

func (*TSC_Periph) G4_IO1 

func (p *TSC_Periph) G4_IO1() RMIOCCR

func (*TSC_Periph) G4_IO2 

func (p *TSC_Periph) G4_IO2() RMIOCCR

func (*TSC_Periph) G4_IO3 

func (p *TSC_Periph) G4_IO3() RMIOCCR

func (*TSC_Periph) G4_IO4 

func (p *TSC_Periph) G4_IO4() RMIOCCR

func (*TSC_Periph) G5E 

func (p *TSC_Periph) G5E() RMIOGCSR

func (*TSC_Periph) G5S 

func (p *TSC_Periph) G5S() RMIOGCSR

func (*TSC_Periph) G5_IO1 

func (p *TSC_Periph) G5_IO1() RMIOCCR

func (*TSC_Periph) G5_IO2 

func (p *TSC_Periph) G5_IO2() RMIOCCR

func (*TSC_Periph) G5_IO3 

func (p *TSC_Periph) G5_IO3() RMIOCCR

func (*TSC_Periph) G5_IO4 

func (p *TSC_Periph) G5_IO4() RMIOCCR

func (*TSC_Periph) G6E 

func (p *TSC_Periph) G6E() RMIOGCSR

func (*TSC_Periph) G6S 

func (p *TSC_Periph) G6S() RMIOGCSR

func (*TSC_Periph) G6_IO1 

func (p *TSC_Periph) G6_IO1() RMIOCCR

func (*TSC_Periph) G6_IO2 

func (p *TSC_Periph) G6_IO2() RMIOCCR

func (*TSC_Periph) G6_IO3 

func (p *TSC_Periph) G6_IO3() RMIOCCR

func (*TSC_Periph) G6_IO4 

func (p *TSC_Periph) G6_IO4() RMIOCCR

func (*TSC_Periph) G7E 

func (p *TSC_Periph) G7E() RMIOGCSR

func (*TSC_Periph) G7S 

func (p *TSC_Periph) G7S() RMIOGCSR

func (*TSC_Periph) G7_IO1 

func (p *TSC_Periph) G7_IO1() RMIOCCR

func (*TSC_Periph) G7_IO2 

func (p *TSC_Periph) G7_IO2() RMIOCCR

func (*TSC_Periph) G7_IO3 

func (p *TSC_Periph) G7_IO3() RMIOCCR

func (*TSC_Periph) G7_IO4 

func (p *TSC_Periph) G7_IO4() RMIOCCR

func (*TSC_Periph) G8E 

func (p *TSC_Periph) G8E() RMIOGCSR

func (*TSC_Periph) G8S 

func (p *TSC_Periph) G8S() RMIOGCSR

func (*TSC_Periph) G8_IO1 

func (p *TSC_Periph) G8_IO1() RMIOCCR

func (*TSC_Periph) G8_IO2 

func (p *TSC_Periph) G8_IO2() RMIOCCR

func (*TSC_Periph) G8_IO3 

func (p *TSC_Periph) G8_IO3() RMIOCCR

func (*TSC_Periph) G8_IO4 

func (p *TSC_Periph) G8_IO4() RMIOCCR

func (*TSC_Periph) IODEF 

func (p *TSC_Periph) IODEF() RMCR

func (*TSC_Periph) MCEF 

func (p *TSC_Periph) MCEF() RMISR

func (*TSC_Periph) MCEIC 

func (p *TSC_Periph) MCEIC() RMICR

func (*TSC_Periph) MCEIE 

func (p *TSC_Periph) MCEIE() RMIER

func (*TSC_Periph) MCV 

func (p *TSC_Periph) MCV() RMCR

func (*TSC_Periph) PGPSC 

func (p *TSC_Periph) PGPSC() RMCR

func (*TSC_Periph) SSD 

func (p *TSC_Periph) SSD() RMCR

func (*TSC_Periph) SSE 

func (p *TSC_Periph) SSE() RMCR

func (*TSC_Periph) SSPSC 

func (p *TSC_Periph) SSPSC() RMCR

func (*TSC_Periph) START 

func (p *TSC_Periph) START() RMCR

func (*TSC_Periph) SYNCPOL 

func (p *TSC_Periph) SYNCPOL() RMCR

func (*TSC_Periph) TSCE 

func (p *TSC_Periph) TSCE() RMCR

Source Files

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