m68kemu

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 Go to latest Published: Sep 8, 2026 License: MIT Imports: 7 Imported by: 0

README

m68kemu

A Motorola 68000 emulator written in Go.

This project provides a Motorola 68000 CPU emulator for retro-computing projects, with a current focus on becoming part of an Atari ST emulator. The core aims to be timing-aware, testable, and easy to embed in a larger machine model.

Features

  • Motorola 68000 instruction set emulation.
  • Timing-aware execution with per-instruction cycle accounting.
  • Supervisor and user modes.
  • Interrupt handling and exception processing.
  • Correct short exception frames for group 1/2 exceptions and 68000 group 0 bus/address error frames.
  • 24-bit address bus with support for multiple devices, fixed-range mappings, and Atari ST-style region layout.
  • Tracing, breakpoints, cycle-budgeted execution, and verbose logging helpers with instruction-range disassembly.
  • Rich debug hooks for per-instruction trace, pre-instruction snapshots, exceptions, bus accesses, and accepted interrupts.
  • RunUntil stop conditions for instruction budgets, exact PC stops, PC ranges, exceptions, bus-access matches, and custom predicates.
  • Optional rolling debug history plus helpers to inspect the last exception stack frame.
  • Optional cycle scheduler hooks for machine-level devices such as timers, video, DMA, and interrupt controllers.

Current Status

The CPU core is in good shape for integration work:

  • Instruction execution, stack behavior, interrupts, and most commonly used addressing modes are covered by tests.
  • RESET now follows machine-friendly semantics for an Atari ST integration: the CPU instruction resets attached devices but does not erase RAM contents.
  • Bus and address faults now use the richer 68000 group 0 stack frame, which is important for realistic system error handling.
  • The bus has fast paths for simple memory setups and fixed-range mappings, which keeps the core practical for full-machine emulation.

Still missing for a complete Atari ST:

  • Prefetch-sensitive behavior and any remaining compatibility gaps found by larger TOS / software workloads.

Getting Started

This package is designed to be used as a library in your own projects.

The repository also includes a small example command in cmd/qsortdemo, which assembles and executes the testdata/qsort.s quicksort demo.

Requirements

This module targets Go 1.26.

Installation
go get github.com/jenska/m68kemu

If you want the demo binary, install it directly:

go install github.com/jenska/m68kemu/cmd/qsortdemo@latest
Example Usage

Here's a simple example of how to set up the CPU, load a program, and run it:

package main

import (
 "fmt"
 "log"

 "github.com/jenska/m68kemu"
)

func main() {
 // Create a 64KB RAM device at address 0.
 ram := m68kemu.NewRAM(0, 64*1024)

 // Create a bus and attach the RAM.
 bus := m68kemu.NewBus(ram)

 // Set up the initial stack pointer and program counter.
 // SSP at 0x1000, PC at 0x2000.
 ram.Write(m68kemu.Long, 0, 0x1000)
 ram.Write(m68kemu.Long, 4, 0x2000)

 // Create the CPU.
 cpu, err := m68kemu.NewCPU(bus)
 if err != nil {
  log.Fatalf("Failed to create CPU: %v", err)
 }

 // Assemble a simple program: MOVEQ #5, D0 (opcode 0x7005)
 program := []byte{0x70, 0x05}
 startPC, _ := ram.Read(m68kemu.Long, 4)

 for i, b := range program {
  if err := ram.Write(m68kemu.Byte, startPC+uint32(i), uint32(b)); err != nil {
   log.Fatalf("Failed to write program: %v", err)
  }
 }

 // Step one instruction.
 if err := cpu.Step(); err != nil {
  log.Fatalf("CPU step failed: %v", err)
 }

 // Print registers to see the result.
 regs := cpu.Registers()
 fmt.Printf("D0 = %d\n", regs.D[0]) // Should be 5
 fmt.Printf("PC = 0x%04x\n", regs.PC) // Should be 0x2002
}
Cycle Scheduler

Machine devices can follow CPU time by attaching a scheduler:

scheduler := m68kemu.NewCycleScheduler()
cpu.SetScheduler(scheduler)

scheduler.ScheduleAfter(512, func(now uint64) {
 // Run a timer tick, trigger an interrupt, advance video state, etc.
})

The scheduler is intentionally small at this stage. It is meant as a foundation for ST components rather than a finished machine-timing framework.

Verbose Logging And Range Disassembly

The emulator includes helpers for both one-off disassembly and trace logging:

logger := m68kemu.NewVerboseLogger(cpu, bus, os.Stdout, m68kemu.VerboseLoggerOptions{
  IncludeRegisters: true,
  IncludeCycles:    true,
  MemoryRanges: []m68kemu.MemoryRange{
    {Start: 0x2000, Length: 0x10, Label: "program"},
  },
})
cpu.SetTracer(logger.Trace)

lines, err := m68kemu.DisassembleMemoryRange(bus, 0x2000, 0x10)
if err != nil {
 log.Fatalf("disassembly failed: %v", err)
}
for _, line := range lines {
 fmt.Println(line)
}

Verbose trace lines include the current PC, decoded assembly, and optionally the total cycle count. When the tracer has access to the fetched instruction bytes, the logger also includes the raw opcode and per-instruction cycle delta, for example:

TRACE PC 00002000 OPCODE 7005 DELTA 4 CYCLES 4 MOVEQ #5, D0

These helpers use the bus Peek path when available so debug output does not trigger device side effects, and the verbose logger prefers TraceInfo.Bytes for disassembly so the trace remains accurate even when fetch-side effects would make a second bus read misleading.

Debug Hooks

For emulator bring-up and TOS failure analysis, the CPU exposes several debugger-oriented callbacks:

cpu.SetPreTracer(func(info m68kemu.PreTraceInfo) {
 // Inspect registers before the instruction executes.
})

cpu.SetTracer(func(info m68kemu.TraceInfo) {
 // Instruction address, opcode bytes, mnemonic, before/after registers,
 // per-instruction cycle delta, and total cycle count.
})

cpu.SetExceptionTracer(func(info m68kemu.ExceptionInfo) {
 // Vector, trapping opcode address, stacked/reported PC, SR before/after,
 // new handler PC, and decoded stack-frame details.
})

cpu.SetBusTracer(func(info m68kemu.BusAccessInfo) {
 // Address, size, read/write, value, instruction-fetch flag, and current instruction PC.
})

cpu.SetInterruptTracer(func(info m68kemu.InterruptInfo) {
 // Accepted IRQ level, vector, autovector/explicit, and PC/SR at acceptance.
})

RunUntil can also stop on richer conditions:

result, err := cpu.RunUntil(m68kemu.RunUntilOptions{
 MaxInstructions: 1000,
 StopAtPC:        []uint32{0x00fc1234},
 StopOnException: true,
 StopOnBusAccess: func(info m68kemu.BusAccessInfo) bool {
  return !info.InstructionFetch && info.Address == 0x00ff8209
 },
 StopPredicate: func(info m68kemu.RunPredicateInfo) bool {
  return info.Registers.D[0] == 0xdeadbeef
 },
})

If you want a rolling "what just happened?" buffer without always logging, call cpu.SetHistoryLimit(n) and inspect cpu.History(). After an exception, cpu.CurrentExceptionFrame() and m68kemu.ReadExceptionStackFrame(...) can decode the pushed 68000 frame directly from memory.

Testing

The emulator has an extensive test suite, including instruction-level tests and small programs.

To run the tests:

go test ./...

To run the benchmarks:

go test -bench=. ./...

To run the core CPU and infrastructure benchmarks without test noise:

go test -run '^$' -bench 'Benchmark(BubbleSort|PrimeSieve|RunEightMillionCycles|RecursiveFibonacci|CycleSchedulerAdvanceBurst|BusReadMappedRanges)$' -benchmem ./...

Performance Notes

Recent profiling work focused on the interpreter hot path:

  • bus fast paths for simple and fixed-range mappings
  • cached single-RAM fast path when the bus has no wait-state devices
  • precomputed page-range lookup for mapped devices
  • amortized scheduler event dispatch without per-event slice shifting
  • reduced wait-state overhead when no device contributes extra wait states
  • fewer allocations and less debug bookkeeping in normal benchmark loops
  • predecoded opcode metadata for common decode fields
  • Go 1.26 benchmark loops using testing.B.Loop

Representative results on June 13, 2026 on Apple M1 (darwin/arm64, Go 1.26.3) were:

  • BenchmarkBubbleSort: ~2.54 ms/op
  • BenchmarkPrimeSieve: ~4.98 ms/op
  • BenchmarkRunEightMillionCycles: ~25.6 ms/op
  • BenchmarkRecursiveFibonacci: ~26.5 ms/op
  • BenchmarkCycleSchedulerAdvanceBurst: ~3.29 us/op
  • BenchmarkBusReadMappedRanges: ~15.5 ns/op

See doc/benchmark_report.md for more detail.

License

This project is licensed under the MIT License - see the LICENSE file for details.

Documentation

Index

Constants

View Source 
const (
	Version           = "1.5.0"
	XBusError         = 2
	XAddressError     = 3
	XIllegal          = 4
	XDivByZero        = 5
	XPrivViolation    = 8
	XLineA            = 10
	XLineF            = 11
	XUninitializedInt = 15
	XTrap             = 32
)
View Source 
const AutoVector uint8 = 0

AutoVector is the vector value that asks the CPU to auto-vector an interrupt request (using vector 24+level) instead of taking a device-supplied vector. It is the zero value, so a request with no explicit vector auto-vectors.

Variables

This section is empty.

Functions

This section is empty.

Types

type AddressBus 

type AddressBus interface {
	Read(s Size, address uint32) (uint32, error)
	Write(s Size, address uint32, value uint32) error
	Reset()
}

AddressBus for accessing address areas

type AddressError 

type AddressError uint32

func (AddressError) Error 

func (ae AddressError) Error() string

type AddressRange added in v1.2.0 

type AddressRange struct {
	Start uint32
	End   uint32
}

func (AddressRange) Contains added in v1.2.0 

func (r AddressRange) Contains(address uint32) bool

type AddressRangeDevice added in v1.1.0 

type AddressRangeDevice interface {
	AddressRange() (start uint32, end uint32)
}

AddressRangeDevice exposes a fixed, inclusive address range [start, end].

type Breakpoint 

type Breakpoint struct {
	Address   uint32
	OnExecute bool
	OnRead    bool
	OnWrite   bool
	Halt      bool
	Callback  func(BreakpointEvent) error
}

type BreakpointEvent 

type BreakpointEvent struct {
	Type      BreakpointType
	Address   uint32
	Registers Registers
}

type BreakpointHit 

type BreakpointHit struct {
	Address uint32
	Type    BreakpointType
}

func (BreakpointHit) Error 

func (bh BreakpointHit) Error() string

type BreakpointType 

type BreakpointType int
const (
	BreakpointExecute BreakpointType = iota
	BreakpointRead
	BreakpointWrite
)

func (BreakpointType) String 

func (bt BreakpointType) String() string

type Bus 

type Bus struct {
	// contains filtered or unexported fields
}

Bus multiplexes memory access between attached devices and performs common checks such as alignment and bus error handling.

func NewBus 

func NewBus(devices ...Device) *Bus

NewBus constructs a bus optionally seeded with devices.

func (*Bus) AddDevice 

func (b *Bus) AddDevice(device Device)

AddDevice attaches an additional device to the bus.

func (*Bus) Peek added in v1.1.0 

func (b *Bus) Peek(s Size, address uint32) (uint32, error)

Peek reads from the mapped device without charging wait states. Devices may use this for debugger-friendly, side-effect-free inspection.

func (*Bus) Read 

func (b *Bus) Read(s Size, address uint32) (uint32, error)

Read forwards a read to the mapped device after performing alignment and mapping checks.

func (*Bus) Reset 

func (b *Bus) Reset()

Reset propagates a reset to all attached devices.

func (*Bus) SetWaitStates 

func (b *Bus) SetWaitStates(states uint32)

SetWaitStates sets the base wait-state count charged to the CPU for every bus transaction. A device may add to it by implementing WaitStateDevice.

func (*Bus) Write 

func (b *Bus) Write(s Size, address uint32, value uint32) error

Write forwards a write to the mapped device after performing alignment and mapping checks.

type BusAccessCallback added in v1.2.0 

type BusAccessCallback func(BusAccessInfo)

type BusAccessInfo added in v1.2.0 

type BusAccessInfo struct {
	Address          uint32
	Size             Size
	Value            uint32
	Write            bool
	InstructionFetch bool
	PC               uint32
}

BusAccessInfo describes one memory transaction observed by the CPU core.

type BusError 

type BusError uint32

func (BusError) Error 

func (be BusError) Error() string

type CPU 

type CPU interface {
	// Execution.
	Reset() error
	Step() error
	RunCycles(budget uint64) error
	RunInstructions(count uint64) error
	RunUntil(options RunUntilOptions) (RunResult, error)
	Cycles() uint64

	// State inspection.
	Registers() Registers
	DebugState() DebugState
	CurrentExceptionFrame() (ExceptionStackFrame, bool, error)

	// External wiring.
	RequestInterrupt(level, vector uint8) error
	SetIRQSource(IRQSource)
	SetScheduler(*CycleScheduler)
	Scheduler() *CycleScheduler
	SetFastMemory(...FastRegion)

	// Observation and debugging.
	SetHooks(Hooks)
	Hooks() Hooks
	SetTracer(TraceCallback)
	SetBusTracer(BusAccessCallback)
	SetExceptionTracer(ExceptionCallback)
	AddBreakpoint(Breakpoint)
	SetHistoryLimit(limit int)
	History() []HistoryEntry
}

CPU is the interface returned by NewCPU for driving the emulator core.

func NewCPU 

func NewCPU(bus *Bus, opts ...Option) (CPU, error)

NewCPU builds a CPU bound to bus. By default it performs a reset (reading the vector from the bus); pass WithDeferredReset to skip that.

type ContainsDevice added in v1.5.0 

type ContainsDevice interface {
	Contains(address uint32) bool
}

ContainsDevice decides, per address, whether the device answers for it.

type CycleListener added in v1.1.0 

type CycleListener interface {
	AdvanceCycles(delta uint64, now uint64)
}

type CycleScheduler added in v1.1.0 

type CycleScheduler struct {
	// contains filtered or unexported fields
}

func NewCycleScheduler added in v1.2.0 

func NewCycleScheduler() *CycleScheduler

func (*CycleScheduler) AddListener added in v1.2.0 

func (s *CycleScheduler) AddListener(listener CycleListener)

func (*CycleScheduler) Advance added in v1.2.0 

func (s *CycleScheduler) Advance(cpuDelta uint64)

func (*CycleScheduler) Now added in v1.2.0 

func (s *CycleScheduler) Now() uint64

func (*CycleScheduler) Reset added in v1.2.0 

func (s *CycleScheduler) Reset(now uint64)

func (*CycleScheduler) Schedule added in v1.2.0 

func (s *CycleScheduler) Schedule(at uint64, fn func(now uint64))

func (*CycleScheduler) ScheduleAfter added in v1.2.0 

func (s *CycleScheduler) ScheduleAfter(delta uint64, fn func(now uint64))

func (*CycleScheduler) SetClockRatio added in v1.5.0 

func (s *CycleScheduler) SetClockRatio(deviceHz, cpuHz uint64)

SetClockRatio makes scheduler time (Now, listener deltas, and event "at" values) run in device cycles rather than CPU cycles: an Advance of n CPU cycles then moves scheduler time by n*deviceHz/cpuHz, carrying the sub-cycle remainder. Passing 0 for either argument, or never calling this, keeps the default 1:1 ratio.

type DebugFaultInfo added in v1.2.0 

type DebugFaultInfo struct {
	Address          uint32
	PC               uint32
	Opcode           uint16
	FunctionCode     uint16
	Write            bool
	InstructionFetch bool
	Valid            bool
}

type DebugState added in v1.2.0 

type DebugState struct {
	Registers     Registers
	InException   bool
	InterruptMask uint8
	LastFault     DebugFaultInfo
	LastException ExceptionInfo
	HasException  bool
	LastInterrupt InterruptInfo
	HasInterrupt  bool
}

type Device 

type Device interface {
	Read(Size, uint32) (uint32, error)
	Write(Size, uint32, uint32) error
	Reset()
}

Device represents a memory-mapped peripheral on the address bus. Implementations must be safe for repeated Reset calls.

A device must also be locatable: implement AddressRangeDevice for a single contiguous span, or ContainsDevice for a non-contiguous or state-dependent decode (a device may implement both, in which case Contains decides membership and AddressRange only bounds it).

func MapDevice added in v1.1.0 

func MapDevice(start, end uint32, device Device) Device

type DisassemblyLine added in v1.2.0 

type DisassemblyLine struct {
	Address  uint32
	Bytes    []byte
	Assembly string
}

DisassemblyLine captures one decoded instruction plus the backing bytes.

func DisassembleInstruction added in v1.2.0 

func DisassembleInstruction(bus AddressBus, address uint32) (DisassemblyLine, error)

DisassembleInstruction decodes one instruction at the given bus address.

func DisassembleMemoryRange added in v1.2.0 

func DisassembleMemoryRange(bus AddressBus, start uint32, length uint32) ([]DisassemblyLine, error)

DisassembleMemoryRange decodes instructions sequentially until the range is covered.

func (DisassemblyLine) String added in v1.2.0 

func (line DisassemblyLine) String() string

String renders a disassembly line with its bytes for human-readable logs.

type ExceptionCallback added in v1.2.0 

type ExceptionCallback func(ExceptionInfo)

type ExceptionInfo added in v1.2.0 

type ExceptionInfo struct {
	Vector        uint32
	PC            uint32
	NewPC         uint32
	Opcode        uint16
	OpcodeAddress uint32
	FaultAddress  uint32
	FaultValid    bool
	SR            uint16
	NewSR         uint16
	StackPointer  uint32
	Frame         ExceptionStackFrame
	FrameValid    bool
	InterruptMask uint8
	Group0        bool
}

ExceptionInfo describes one taken exception after vectoring has completed.

type ExceptionStackFrame added in v1.2.3 

type ExceptionStackFrame struct {
	Format              ExceptionStackFrameFormat
	StackPointer        uint32
	StatusWord          uint16
	FaultAddress        uint32
	InstructionRegister uint16
	SR                  uint16
	PC                  uint32
}

ExceptionStackFrame mirrors the exception frame currently stored on the supervisor stack.

func ReadExceptionStackFrame added in v1.2.3 

func ReadExceptionStackFrame(bus AddressBus, sp uint32, format ExceptionStackFrameFormat) (ExceptionStackFrame, error)

ReadExceptionStackFrame decodes a 68000 exception frame directly from memory without requiring the caller to know the byte layout.

type ExceptionStackFrameFormat added in v1.2.3 

type ExceptionStackFrameFormat int

ExceptionStackFrameFormat identifies the 68000 frame layout captured for an exception. 

const (
	ExceptionStackFrameGroup12 ExceptionStackFrameFormat = iota
	ExceptionStackFrameGroup0
)

type FastRegion added in v1.5.0 

type FastRegion struct {
	Base       uint32
	Mem        []byte
	WaitStates uint32
	ReadOnly   bool
}

FastRegion describes one flat, directly-addressable span of guest memory the interpreter may service without going through the bus, for data reads, data writes (unless ReadOnly), and instruction/operand fetches whose whole access falls inside [Base, Base+len(Mem)).

The caller guarantees that, while the region is installed, it behaves as plain memory: accesses have no side effects, the address is not remapped (no MMU banking, no overlay), and Mem is the live backing store (the core reads and, when not ReadOnly, writes it in place). Accesses not fully contained in any region fall through to the bus unchanged, and a write to a ReadOnly region also falls through, so it is safe to map only the sub-range that currently satisfies these guarantees and to re-install the set whenever that changes.

WaitStates is the per-word-transfer penalty the bus would otherwise charge for this region (bus wait states plus the device's fixed contribution). It is added to the cycle counter on every access, doubled for a long access to match the bus running that as two word cycles. Address-dependent penalties (e.g. video bus contention) are not modelled on a fast region; leave such ranges on the bus if they must stay cycle-exact.

Regions are bypassed automatically whenever a breakpoint or bus/instruction tracer is active, so debugging still observes every access.

type HistoryEntry added in v1.2.3 

type HistoryEntry struct {
	Kind      HistoryKind
	Trace     TraceInfo
	Exception ExceptionInfo
	Interrupt InterruptInfo
	BusAccess BusAccessInfo
}

HistoryEntry stores one recent debug event in the optional rolling history buffer.

type HistoryKind added in v1.2.3 

type HistoryKind int
const (
	HistoryInstruction HistoryKind = iota
	HistoryException
	HistoryInterrupt
	HistoryBusAccess
)

type Hooks added in v1.5.0 

type Hooks struct {
	Trace     TraceCallback
	PreTrace  PreTraceCallback
	Exception ExceptionCallback
	Bus       BusAccessCallback
	Interrupt InterruptCallback
}

Hooks bundles every observation callback the core supports. A nil field means "no callback". SetHooks installs all of them in one call and runs the internal trace/run-mode refresh exactly once, which lets a caller swap a whole tracing configuration atomically instead of touching five setters.

type IRQSource added in v1.5.0 

type IRQSource interface {
	// PendingIRQ reports the highest interrupt level currently asserted (0 for
	// none) and the vector to take (AutoVector to auto-vector). It is called
	// once per instruction, so it must be cheap.
	PendingIRQ() (level, vector uint8)
	// AckIRQ is called with the level the CPU has just accepted, so the source
	// can lower that line. A source with edge/pulse semantics uses this to clear
	// the request it just delivered.
	AckIRQ(level uint8)
}

IRQSource is a level-sensitive interrupt line the CPU samples at every instruction boundary. It suits a machine whose peripherals hold an interrupt asserted until it is serviced, rather than posting one-shot requests through RequestInterrupt.

type InterruptCallback added in v1.2.3 

type InterruptCallback func(InterruptInfo)

type InterruptInfo added in v1.2.3 

type InterruptInfo struct {
	Level      uint8
	Vector     uint32
	AutoVector bool
	PC         uint32
	NewPC      uint32
	SR         uint16
	NewSR      uint16
}

InterruptInfo describes an interrupt that was accepted by the CPU.

type MemoryRange added in v1.2.0 

type MemoryRange struct {
	Start  uint32
	Length uint32
	Label  string
}

MemoryRange describes a region of memory to disassemble for debug output.

type Option added in v1.5.0 

type Option func(*cpuConfig)

Option configures CPU construction. Pass options to NewCPU.

func WithDeferredReset added in v1.5.0 

func WithDeferredReset() Option

WithDeferredReset skips the implicit Reset performed by NewCPU. The caller must invoke Reset explicitly once the bus and every device on it are fully wired. Use this when the reset vector is not readable at construction time, for example when the ROM that supplies it is attached to the bus after the CPU is created.

type PeekDevice added in v1.1.0 

type PeekDevice interface {
	Peek(Size, uint32) (uint32, error)
}

PeekDevice exposes a side-effect-free read path for debugging and disassembly.

type PreTraceCallback added in v1.2.3 

type PreTraceCallback func(PreTraceInfo)

type PreTraceInfo added in v1.2.3 

type PreTraceInfo struct {
	PC        uint32
	SR        uint16
	Registers Registers
	Opcode    uint16
	Bytes     []byte
	Mnemonic  string
	Cycles    uint64
}

PreTraceInfo reports an instruction just before execution.

type RAM 

type RAM struct {
	// contains filtered or unexported fields
}

simple flat memory structure

func NewRAM 

func NewRAM(offset, size uint32) *RAM

func (*RAM) AddressRange added in v1.2.0 

func (ram *RAM) AddressRange() (uint32, uint32)

func (*RAM) Contains 

func (ram *RAM) Contains(address uint32) bool

func (*RAM) Peek added in v1.2.0 

func (ram *RAM) Peek(s Size, address uint32) (uint32, error)

func (*RAM) Read 

func (ram *RAM) Read(s Size, address uint32) (uint32, error)

func (*RAM) Reset 

func (ram *RAM) Reset()

func (*RAM) Write 

func (ram *RAM) Write(s Size, address uint32, value uint32) error

type Registers 

type Registers struct {
	D   [8]int32
	A   [8]uint32
	PC  uint32
	SR  uint16
	SSP uint32
	USP uint32
	IR  uint16 // instruction register
}

Registers represents the programmer visible registers of the 68000 CPU.

func (*Registers) String 

func (regs *Registers) String() string

type RunPredicateInfo added in v1.2.3 

type RunPredicateInfo struct {
	Registers     Registers
	Instructions  uint64
	Cycles        uint64
	LastException ExceptionInfo
	HasException  bool
	LastBusAccess BusAccessInfo
	HasBusAccess  bool
	LastInterrupt InterruptInfo
	HasInterrupt  bool
}

RunPredicateInfo is passed to StopPredicate after each completed instruction.

type RunResult added in v1.2.0 

type RunResult struct {
	Reason       RunStopReason
	Instructions uint64
	Cycles       uint64
	PC           uint32
	Exception    ExceptionInfo
	HasException bool
	BusAccess    BusAccessInfo
	HasBusAccess bool
	Interrupt    InterruptInfo
	HasInterrupt bool
}

RunResult reports why RunUntil stopped and what the CPU observed while stopping.

type RunStopReason added in v1.2.0 

type RunStopReason int
const (
	RunStopNone RunStopReason = iota
	RunStopInstructionLimit
	RunStopPC
	RunStopPCInRange
	RunStopPCOutsideRange
	RunStopBusAccess
	RunStopPredicate
	RunStopException
	RunStopIllegalOpcode
)

func (RunStopReason) String added in v1.2.0 

func (reason RunStopReason) String() string

type RunUntilOptions added in v1.2.0 

type RunUntilOptions struct {
	MaxInstructions   uint64
	StopOnException   bool
	StopOnIllegal     bool
	StopAtPC          []uint32
	StopOnPCRange     *AddressRange
	StopWhenPCOutside *AddressRange
	StopOnBusAccess   func(BusAccessInfo) bool
	StopPredicate     func(RunPredicateInfo) bool
}

RunUntilOptions controls which conditions stop the instruction runner.

type Size 

type Size uint32
const (
	Byte Size = 1
	Word Size = 2
	Long Size = 4
)

type TraceCallback 

type TraceCallback func(TraceInfo)

type TraceInfo 

type TraceInfo struct {
	PC              uint32
	SR              uint16
	Registers       Registers
	BeforeRegisters Registers
	Opcode          uint16
	Bytes           []byte
	Mnemonic        string
	CycleDelta      uint32
	Cycles          uint64
}

TraceInfo reports the outcome of a single executed instruction.

type VerboseLogger added in v1.2.0 

type VerboseLogger struct {
	// contains filtered or unexported fields
}

VerboseLogger formats trace callbacks with disassembly and optional state dumps.

func NewVerboseLogger added in v1.2.0 

func NewVerboseLogger(cpu CPU, bus AddressBus, writer io.Writer, options VerboseLoggerOptions) *VerboseLogger

NewVerboseLogger builds a trace callback helper that writes detailed execution logs.

func (*VerboseLogger) Trace added in v1.2.0 

func (logger *VerboseLogger) Trace(info TraceInfo)

Trace implements TraceCallback for use with CPU.SetTracer.

type VerboseLoggerOptions added in v1.2.0 

type VerboseLoggerOptions struct {
	IncludeRegisters bool
	IncludeCycles    bool
	MemoryRanges     []MemoryRange
}

VerboseLoggerOptions controls how much detail a VerboseLogger emits.

type WaitStateDevice 

type WaitStateDevice interface {
	WaitStates(Size, uint32) uint32
}

WaitStateDevice optionally advertises additional wait states a device imposes per transaction. Implementations may vary their contribution based on access size and address.

Source Files

View all Source files

Directories

Path Synopsis
cmd
qsortdemo command

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