Documentation
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Overview ¶
Package uxn provides an implementation of a Uxn CPU, called Machine, that can be used to execute Uxn bytecode.
Index ¶
Constants ¶
This section is empty.
Variables ¶
var ErrBRK = errors.New("BRK")
Functions ¶
This section is empty.
Types ¶
type Device ¶
type Device interface {
In(port byte) (value byte)
InShort(port byte) (value uint16)
Out(port, value byte)
OutShort(port byte, value uint16)
}
Device provides access to external systems connected to the Uxn CPU.
type HaltError ¶
HaltError is returned by Exec if execution is halted by the program for some reason.
type Machine ¶
Machine is an implementation of a Uxn CPU.
func NewMachine ¶
NewMachine returns a Uxn CPU loaded with the given rom at 0x100. If the rom is larger than 0xfeff bytes then Mem is grown to accommodate it, even though the Uxn CPU cannot directly address the extra memory.
func (*Machine) Exec ¶
Exec executes the intsruction at m.PC. It returns ErrBRK if that instruction is BRK, and otherwise only returns a non-nil error if it encounters a halt condition.
func (*Machine) OpAddr ¶
OpAddr returns the address associated with the operation at addr, either from memory or the stack, and reports whether the operation has an associated address (for example, JMP does while POP does not), and whether there are enough bytes on the stack to provide an address (ie, it returns false if executing the instruction would trigger a stack underflow).
type Op ¶
type Op byte
Op represents a Uxn opcode.
const ( BRK Op = iota INC POP NIP SWP ROT DUP OVR EQU NEQ GTH LTH JMP JCN JSR STH LDZ STZ LDR STR LDA STA DEI DEO ADD SUB MUL DIV AND ORA EOR SFT JCI INC2 POP2 NIP2 SWP2 ROT2 DUP2 OVR2 EQU2 NEQ2 GTH2 LTH2 JMP2 JCN2 JSR2 STH2 LDZ2 STZ2 LDR2 STR2 LDA2 STA2 DEI2 DEO2 ADD2 SUB2 MUL2 DIV2 AND2 ORA2 EOR2 SFT2 JMI INCr POPr NIPr SWPr ROTr DUPr OVRr EQUr NEQr GTHr LTHr JMPr JCNr JSRr STHr LDZr STZr LDRr STRr LDAr STAr DEIr DEOr ADDr SUBr MULr DIVr ANDr ORAr EORr SFTr JSI INC2r POP2r NIP2r SWP2r ROT2r DUP2r OVR2r EQU2r NEQ2r GTH2r LTH2r JMP2r JCN2r JSR2r STH2r LDZ2r STZ2r LDR2r STR2r LDA2r STA2r DEI2r DEO2r ADD2r SUB2r MUL2r DIV2r AND2r ORA2r EOR2r SFT2r LIT INCk POPk NIPk SWPk ROTk DUPk OVRk EQUk NEQk GTHk LTHk JMPk JCNk JSRk STHk LDZk STZk LDRk STRk LDAk STAk DEIk DEOk ADDk SUBk MULk DIVk ANDk ORAk EORk SFTk LIT2 INC2k POP2k NIP2k SWP2k ROT2k DUP2k OVR2k EQU2k NEQ2k GTH2k LTH2k JMP2k JCN2k JSR2k STH2k LDZ2k STZ2k LDR2k STR2k LDA2k STA2k DEI2k DEO2k ADD2k SUB2k MUL2k DIV2k AND2k ORA2k EOR2k SFT2k LITr INCkr POPkr NIPkr SWPkr ROTkr DUPkr OVRkr EQUkr NEQkr GTHkr LTHkr JMPkr JCNkr JSRkr STHkr LDZkr STZkr LDRkr STRkr LDAkr STAkr DEIkr DEOkr ADDkr SUBkr MULkr DIVkr ANDkr ORAkr EORkr SFTkr LIT2r INC2kr POP2kr NIP2kr SWP2kr ROT2kr DUP2kr OVR2kr EQU2kr NEQ2kr GTH2kr LTH2kr JMP2kr JCN2kr JSR2kr STH2kr LDZ2kr STZ2kr LDR2kr STR2kr LDA2kr STA2kr DEI2kr DEO2kr ADD2kr SUB2kr MUL2kr DIV2kr AND2kr ORA2kr EOR2kr SFT2kr )
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