## Abstract

Historically, signed-digit adders have been thought of as being logically very complicated to implement, while carry-save adders have been considered to be fast, low power and easy to implement. While the latter is true, the former is a misconception. We show that for every integer k≥1, it is possible to build a network of radix-2^{k} signed-digit adders having the same logical complexity and hence the same area, delay and power consumption as a network of k-bit carry-sum adders (where, a 1-bit carry-sum adder is a carry-save adder). We also study the power and delay tradeoffs involved in using a network of carry-save and signed-digit adders for adding multiple operands when compared to a fast two's-complement adder and show that it always consumes less power. However, when the number of operands is large (>26), a tree of fast carry-lookahead adders was found to be faster.

Original language | English (US) |
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Pages | 15-20 |

Number of pages | 6 |

State | Published - Jan 1 1995 |

Event | Proceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA Duration: Apr 23 1995 → Apr 26 1995 |

### Conference

Conference | Proceedings of the 1995 International Symposium on Low Power Design |
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City | Dana Point, CA, USA |

Period | 4/23/95 → 4/26/95 |

## All Science Journal Classification (ASJC) codes

- Engineering(all)