amd64

package

v1.0.0-pre.1 Latest Latest Go to latest Published: Sep 1, 2022 License: Apache-2.0 Imports: 6 Imported by: 0

Details

Valid go.mod file

The Go module system was introduced in Go 1.11 and is the official dependency management solution for Go.
Redistributable license

Redistributable licenses place minimal restrictions on how software can be used, modified, and redistributed.
Tagged version

Modules with tagged versions give importers more predictable builds.
Stable version

When a project reaches major version v1 it is considered stable.
Learn more about best practices

Repository

github.com/tetratelabs/wazero

Documentation ¶

Index ¶

Constants
Variables
func FitIn32bit(v int64) bool
func InstructionName(instruction asm.Instruction) string
func IsVectorRegister(r asm.Register) bool
func RegisterName(reg asm.Register) string
type Assembler
type AssemblerImpl
- func NewAssembler() *AssemblerImpl
type RexPrefix

Constants ¶

View Source

const (
	// ConditionalRegisterStateE is the e (equal to zero) condition code
	ConditionalRegisterStateE = asm.ConditionalRegisterStateUnset + 1 + iota // ZF equal to zero
	// ConditionalRegisterStateNE is the ne (not equal to zero) condition code
	ConditionalRegisterStateNE // ˜ZF not equal to zero
	// ConditionalRegisterStateS is the s (negative) condition code
	ConditionalRegisterStateS // SF negative
	// ConditionalRegisterStateNS is the ns (non-negative) condition code
	ConditionalRegisterStateNS // ˜SF non-negative
	// ConditionalRegisterStateG is the g (greater) condition code
	ConditionalRegisterStateG // ˜(SF xor OF) & ˜ ZF greater (signed >)
	// ConditionalRegisterStateGE is the ge (greater or equal) condition code
	ConditionalRegisterStateGE // ˜(SF xor OF) greater or equal (signed >=)
	// ConditionalRegisterStateL is the l (less) condition code
	ConditionalRegisterStateL // SF xor OF less (signed <)
	// ConditionalRegisterStateLE is the le (less or equal) condition code
	ConditionalRegisterStateLE // (SF xor OF) | ZF less or equal (signed <=)
	// ConditionalRegisterStateA is the a (above) condition code
	ConditionalRegisterStateA // ˜CF & ˜ZF above (unsigned >)
	// ConditionalRegisterStateAE is the ae (above or equal) condition code
	ConditionalRegisterStateAE // ˜CF above or equal (unsigned >=)
	// ConditionalRegisterStateB is the b (below) condition code
	ConditionalRegisterStateB // CF below (unsigned <)
	// ConditionalRegisterStateBE is the be (below or equal) condition code
	ConditionalRegisterStateBE // CF | ZF below or equal (unsigned <=)
)

AMD64-specific conditional register states.

See https://www.lri.fr/~filliatr/ens/compil/x86-64.pdf See https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf

View Source

const (
	// NONE is not a real instruction but represents the lack of an instruction
	NONE asm.Instruction = iota
	// ADDL is the ADD instruction in 32-bit mode. https://www.felixcloutier.com/x86/add
	ADDL
	// ADDQ is the ADD instruction in 64-bit mode. https://www.felixcloutier.com/x86/add
	ADDQ
	// ADDSD is the ADDSD instruction. https://www.felixcloutier.com/x86/addsd
	ADDSD
	// ADDSS is the ADDSS instruction. https://www.felixcloutier.com/x86/addss
	ADDSS
	// ANDL is the AND instruction in 32-bit mode. https://www.felixcloutier.com/x86/and
	ANDL
	// ANDPD is the ANDPD instruction. https://www.felixcloutier.com/x86/andpd
	ANDPD
	// ANDPS is the ANDPS instruction. https://www.felixcloutier.com/x86/andps
	ANDPS
	// ANDQ is the AND instruction in 64-bit mode. https://www.felixcloutier.com/x86/and
	ANDQ
	// BSRL is the BSR instruction in 32-bit mode. https://www.felixcloutier.com/x86/bsr
	BSRL
	// BSRQ is the BSR instruction in 64-bit mode. https://www.felixcloutier.com/x86/bsr
	BSRQ
	// CDQ is the CDQ instruction. https://www.felixcloutier.com/x86/cwd:cdq:cqo
	CDQ
	// CLD is the CLD instruction. https://www.felixcloutier.com/x86/cld
	CLD
	// CMOVQCS is the CMOVC (move if carry) instruction in 64-bit mode. https://www.felixcloutier.com/x86/cmovcc
	CMOVQCS
	// CMPL is the CMP instruction in 32-bit mode. https://www.felixcloutier.com/x86/cmp
	CMPL
	// CMPQ is the CMP instruction in 64-bit mode. https://www.felixcloutier.com/x86/cmp
	CMPQ
	// COMISD is the COMISD instruction. https://www.felixcloutier.com/x86/comisd
	COMISD
	// COMISS is the COMISS instruction. https://www.felixcloutier.com/x86/comiss
	COMISS
	// CQO is the CQO instruction. https://www.felixcloutier.com/x86/cwd:cdq:cqo
	CQO
	// CVTSD2SS is the CVTSD2SS instruction. https://www.felixcloutier.com/x86/cvtsd2ss
	CVTSD2SS
	// CVTSL2SD is the CVTSI2SD instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvtsi2sd
	CVTSL2SD
	// CVTSL2SS is the CVTSI2SS instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvtsi2ss
	CVTSL2SS
	// CVTSQ2SD is the CVTSI2SD instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvtsi2sd
	CVTSQ2SD
	// CVTSQ2SS is the CVTSI2SS instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvtsi2ss
	CVTSQ2SS
	// CVTSS2SD is the CVTSS2SD instruction. https://www.felixcloutier.com/x86/cvtss2sd
	CVTSS2SD
	// CVTTSD2SL is the CVTTSD2SI instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvttsd2si
	CVTTSD2SL
	// CVTTSD2SQ is the CVTTSD2SI instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvttsd2si
	CVTTSD2SQ
	// CVTTSS2SL is the CVTTSS2SI instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvttss2si
	CVTTSS2SL
	// CVTTSS2SQ is the CVTTSS2SI instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvttss2si
	CVTTSS2SQ
	// DECQ is the DEC instruction in 64-bit mode. https://www.felixcloutier.com/x86/dec
	DECQ
	// DIVL is the DIV instruction in 32-bit mode. https://www.felixcloutier.com/x86/div
	DIVL
	// DIVQ is the DIV instruction in 64-bit mode. https://www.felixcloutier.com/x86/div
	DIVQ
	// DIVSD is the DIVSD instruction. https://www.felixcloutier.com/x86/divsd
	DIVSD
	// DIVSS is the DIVSS instruction. https://www.felixcloutier.com/x86/divss
	DIVSS
	// IDIVL is the IDIV instruction in 32-bit mode. https://www.felixcloutier.com/x86/idiv
	IDIVL
	// IDIVQ is the IDIV instruction in 64-bit mode. https://www.felixcloutier.com/x86/idiv
	IDIVQ
	// INCQ is the INC instruction in 64-bit mode. https://www.felixcloutier.com/x86/inc
	INCQ
	// JCC is the JAE (jump if above or equal) instruction. https://www.felixcloutier.com/x86/jcc
	JCC
	// JCS is the JB (jump if below) instruction. https://www.felixcloutier.com/x86/jcc
	JCS
	// JEQ is the JE (jump if equal) instruction. https://www.felixcloutier.com/x86/jcc
	JEQ
	// JGE is the JGE (jump if greater or equal) instruction. https://www.felixcloutier.com/x86/jcc
	JGE
	// JGT is the JG (jump if greater) instruction. https://www.felixcloutier.com/x86/jcc
	JGT
	// JHI is the JNBE (jump if not below or equal) instruction. https://www.felixcloutier.com/x86/jcc
	JHI
	// JLE is the JLE (jump if less or equal) instruction. https://www.felixcloutier.com/x86/jcc
	JLE
	// JLS is the JNA (jump if not above) instruction. https://www.felixcloutier.com/x86/jcc
	JLS
	// JLT is the JL (jump if less) instruction. https://www.felixcloutier.com/x86/jcc
	JLT
	// JMI is the JS (jump if sign) instruction. https://www.felixcloutier.com/x86/jcc
	JMI
	// JNE is the JNE (jump if not equal) instruction. https://www.felixcloutier.com/x86/jcc
	JNE
	// JPC is the JPO (jump if parity odd) instruction. https://www.felixcloutier.com/x86/jcc
	JPC
	// JPL is the JNS (jump if not sign) instruction. https://www.felixcloutier.com/x86/jcc
	JPL
	// JPS is the JPE (jump if parity even) instruction. https://www.felixcloutier.com/x86/jcc
	JPS
	// LEAQ is the LEA instruction in 64-bit mode. https://www.felixcloutier.com/x86/lea
	LEAQ
	// LZCNTL is the LZCNT instruction in 32-bit mode. https://www.felixcloutier.com/x86/lzcnt
	LZCNTL
	// LZCNTQ is the LZCNT instruction in 64-bit mode. https://www.felixcloutier.com/x86/lzcnt
	LZCNTQ
	// MAXSD is the MAXSD instruction. https://www.felixcloutier.com/x86/maxsd
	MAXSD
	// MAXSS is the MAXSS instruction. https://www.felixcloutier.com/x86/maxss
	MAXSS
	// MINSD is the MINSD instruction. https://www.felixcloutier.com/x86/minsd
	MINSD
	// MINSS is the MINSS instruction. https://www.felixcloutier.com/x86/minss
	MINSS
	// MOVB is the MOV instruction for a single byte. https://www.felixcloutier.com/x86/mov
	MOVB
	// MOVBLSX is the MOVSX instruction for single byte in 32-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
	MOVBLSX
	// MOVBLZX is the MOVZX instruction for single-byte in 32-bit mode. https://www.felixcloutier.com/x86/movzx
	MOVBLZX
	// MOVBQSX is the MOVSX instruction for single byte in 64-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
	MOVBQSX
	// MOVBQZX is the MOVZX instruction for single-byte in 64-bit mode. https://www.felixcloutier.com/x86/movzx
	MOVBQZX
	// MOVL is the MOV instruction for a double word.
	MOVL
	// MOVLQSX is the MOVSXD instruction. https://www.felixcloutier.com/x86/movsx:movsxd
	MOVLQSX
	// MOVLQZX is the MOVZX instruction for a word to a doubleword. https://www.felixcloutier.com/x86/movzx
	MOVLQZX
	// MOVQ is the MOV instruction for a doubleword. https://www.felixcloutier.com/x86/mov
	MOVQ
	// MOVW is the MOV instruction for a word. https://www.felixcloutier.com/x86/mov
	MOVW
	// MOVWLSX is the MOVSX instruction for a word in 32-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
	MOVWLSX
	// MOVWLZX is the MOVZX instruction for a word in 32-bit mode. https://www.felixcloutier.com/x86/movzx
	MOVWLZX
	// MOVWQSX is the MOVSX instruction for a word in 64-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
	MOVWQSX
	// MOVWQZX is the MOVZX instruction for a word in 64-bit mode. https://www.felixcloutier.com/x86/movzx
	MOVWQZX
	// MULL is the MUL instruction in 32-bit mode. https://www.felixcloutier.com/x86/mul
	MULL
	// MULQ is the MUL instruction in 64-bit mode. https://www.felixcloutier.com/x86/mul
	MULQ
	// IMULQ is the IMUL instruction in 64-bit mode. https://www.felixcloutier.com/x86/imul
	IMULQ
	// MULSD is the MULSD instruction. https://www.felixcloutier.com/x86/mulsd
	MULSD
	// MULSS is the MULSS instruction. https://www.felixcloutier.com/x86/mulss
	MULSS
	// NEGQ is the NEG instruction in 64-bit mode. https://www.felixcloutier.com/x86/neg
	NEGQ
	// ORL is the OR instruction in 32-bit mode. https://www.felixcloutier.com/x86/or
	ORL
	// ORPD is the ORPD instruction. https://www.felixcloutier.com/x86/orpd
	ORPD
	// ORPS is the ORPS instruction. https://www.felixcloutier.com/x86/orps
	ORPS
	// ORQ is the OR instruction in 64-bit mode. https://www.felixcloutier.com/x86/or
	ORQ
	// POPCNTL is the POPCNT instruction in 32-bit mode. https://www.felixcloutier.com/x86/popcnt
	POPCNTL
	// POPCNTQ is the POPCNT instruction in 64-bit mode. https://www.felixcloutier.com/x86/popcnt
	POPCNTQ
	// PSLLD is the PSLLD instruction. https://www.felixcloutier.com/x86/psllw:pslld:psllq
	PSLLD
	// PSLLQ is the PSLLQ instruction. https://www.felixcloutier.com/x86/psllw:pslld:psllq
	PSLLQ
	// PSRLD is the PSRLD instruction. https://www.felixcloutier.com/x86/psrlw:psrld:psrlq
	PSRLD
	// PSRLQ is the PSRLQ instruction. https://www.felixcloutier.com/x86/psrlw:psrld:psrlq
	PSRLQ
	// REPMOVSQ is the REP MOVSQ instruction in 64-bit mode. https://www.felixcloutier.com/x86/movs:movsb:movsw:movsd:movsq https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz
	REPMOVSQ
	// REPSTOSQ is the REP STOSQ instruction in 64-bit mode. https://www.felixcloutier.com/x86/stos:stosb:stosw:stosd:stosq https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz
	REPSTOSQ
	// ROLL is the ROL instruction in 32-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror
	ROLL
	// ROLQ is the ROL instruction in 64-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror
	ROLQ
	// RORL is the ROR instruction in 32-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror
	RORL
	// RORQ is the ROR instruction in 64-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror
	RORQ
	// ROUNDSD is the ROUNDSD instruction. https://www.felixcloutier.com/x86/roundsd
	ROUNDSD
	// ROUNDSS is the ROUNDSS instruction. https://www.felixcloutier.com/x86/roundss
	ROUNDSS
	// SARL is the SAR instruction in 32-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr
	SARL
	// SARQ is the SAR instruction in 64-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr
	SARQ
	// SETCC is the SETAE (set if above or equal) instruction. https://www.felixcloutier.com/x86/setcc
	SETCC
	// SETCS is the SETB (set if below) instruction. https://www.felixcloutier.com/x86/setcc
	SETCS
	// SETEQ is the SETE (set if equal) instruction. https://www.felixcloutier.com/x86/setcc
	SETEQ
	// SETGE is the SETGE (set if greater or equal) instruction. https://www.felixcloutier.com/x86/setcc
	SETGE
	// SETGT is the SETG (set if greater) instruction. https://www.felixcloutier.com/x86/setcc
	SETGT
	// SETHI is the SETNBE (set if not below or equal) instruction. https://www.felixcloutier.com/x86/setcc
	SETHI
	// SETLE is the SETLE (set if less or equal) instruction. https://www.felixcloutier.com/x86/setcc
	SETLE
	// SETLS is the SETNA (set if not above) instruction. https://www.felixcloutier.com/x86/setcc
	SETLS
	// SETLT is the SETL (set if less) instruction. https://www.felixcloutier.com/x86/setcc
	SETLT
	// SETMI is the SETS (set if sign) instruction. https://www.felixcloutier.com/x86/setcc
	SETMI
	// SETNE is the SETNE (set if not equal) instruction. https://www.felixcloutier.com/x86/setcc
	SETNE
	// SETPC is the SETNP (set if not parity) instruction. https://www.felixcloutier.com/x86/setcc
	SETPC
	// SETPL is the SETNS (set if not sign) instruction. https://www.felixcloutier.com/x86/setcc
	SETPL
	// SETPS is the SETP (set if parity) instruction. https://www.felixcloutier.com/x86/setcc
	SETPS
	// SHLL is the SHL instruction in 32-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr
	SHLL
	// SHLQ is the SHL instruction in 64-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr
	SHLQ
	// SHRL is the SHR instruction in 32-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr
	SHRL
	// SHRQ is the SHR instruction in 64-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr
	SHRQ
	// SQRTSD is the SQRTSD instruction. https://www.felixcloutier.com/x86/sqrtsd
	SQRTSD
	// SQRTSS is the SQRTSS instruction. https://www.felixcloutier.com/x86/sqrtss
	SQRTSS
	// STD is the STD instruction. https://www.felixcloutier.com/x86/std
	STD
	// SUBL is the SUB instruction in 32-bit mode. https://www.felixcloutier.com/x86/sub
	SUBL
	// SUBQ is the SUB instruction in 64-bit mode. https://www.felixcloutier.com/x86/sub
	SUBQ
	// SUBSD is the SUBSD instruction. https://www.felixcloutier.com/x86/subsd
	SUBSD
	// SUBSS is the SUBSS instruction. https://www.felixcloutier.com/x86/subss
	SUBSS
	// TESTL is the TEST instruction in 32-bit mode. https://www.felixcloutier.com/x86/test
	TESTL
	// TESTQ is the TEST instruction in 64-bit mode. https://www.felixcloutier.com/x86/test
	TESTQ
	// TZCNTL is the TZCNT instruction in 32-bit mode. https://www.felixcloutier.com/x86/tzcnt
	TZCNTL
	// TZCNTQ is the TZCNT instruction in 64-bit mode. https://www.felixcloutier.com/x86/tzcnt
	TZCNTQ
	// UCOMISD is the UCOMISD instruction. https://www.felixcloutier.com/x86/ucomisd
	UCOMISD
	// UCOMISS is the UCOMISS instruction. https://www.felixcloutier.com/x86/ucomisd
	UCOMISS
	// XORL is the XOR instruction in 32-bit mode. https://www.felixcloutier.com/x86/xor
	XORL
	// XORPD is the XORPD instruction. https://www.felixcloutier.com/x86/xorpd
	XORPD
	// XORPS is the XORPS instruction. https://www.felixcloutier.com/x86/xorps
	XORPS
	// XORQ is the XOR instruction in 64-bit mode. https://www.felixcloutier.com/x86/xor
	XORQ
	// XCHGQ is the XCHG instruction in 64-bit mode. https://www.felixcloutier.com/x86/xchg
	XCHGQ
	// RET is the RET instruction. https://www.felixcloutier.com/x86/ret
	RET
	// JMP is the JMP instruction. https://www.felixcloutier.com/x86/jmp
	JMP
	// NOP is the NOP instruction. https://www.felixcloutier.com/x86/nop
	NOP
	// UD2 is the UD2 instruction. https://www.felixcloutier.com/x86/ud
	UD2
	// MOVDQU is the MOVDQU instruction in 64-bit mode. https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64
	MOVDQU
	// MOVDQA is the MOVDQA instruction in 64-bit mode. https://www.felixcloutier.com/x86/movdqa:vmovdqa32:vmovdqa64
	MOVDQA
	// PINSRB is the PINSRB instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq
	PINSRB
	// PINSRW is the PINSRW instruction. https://www.felixcloutier.com/x86/pinsrw
	PINSRW
	// PINSRD is the PINSRD instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq
	PINSRD
	// PINSRQ is the PINSRQ instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq
	PINSRQ
	// PADDB is the PADDB instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq
	PADDB
	// PADDW is the PADDW instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq
	PADDW
	// PADDD is the PADDD instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq
	PADDD
	// PADDQ is the PADDQ instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq
	PADDQ
	// PSUBB is the PSUBB instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd
	PSUBB
	// PSUBW is the PSUBW instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd
	PSUBW
	// PSUBD is the PSUBD instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd
	PSUBD
	// PSUBQ is the PSUBQ instruction. https://www.felixcloutier.com/x86/psubq
	PSUBQ
	// ADDPS is the ADDPS instruction. https://www.felixcloutier.com/x86/addps
	ADDPS
	// ADDPD is the ADDPD instruction. https://www.felixcloutier.com/x86/addpd
	ADDPD
	// SUBPS is the SUBPS instruction. https://www.felixcloutier.com/x86/subps
	SUBPS
	// SUBPD is the SUBPD instruction. https://www.felixcloutier.com/x86/subpd
	SUBPD
	// PMOVSXBW is the PMOVSXBW instruction https://www.felixcloutier.com/x86/pmovsx
	PMOVSXBW
	// PMOVSXWD is the PMOVSXWD instruction https://www.felixcloutier.com/x86/pmovsx
	PMOVSXWD
	// PMOVSXDQ is the PMOVSXDQ instruction https://www.felixcloutier.com/x86/pmovsx
	PMOVSXDQ
	// PMOVZXBW is the PMOVZXBW instruction https://www.felixcloutier.com/x86/pmovzx
	PMOVZXBW
	// PMOVZXWD is the PMOVZXWD instruction https://www.felixcloutier.com/x86/pmovzx
	PMOVZXWD
	// PMOVZXDQ is the PMOVZXDQ instruction https://www.felixcloutier.com/x86/pmovzx
	PMOVZXDQ
	// PSHUFB is the PSHUFB instruction https://www.felixcloutier.com/x86/pshufb
	PSHUFB
	// PSHUFD is the PSHUFD instruction https://www.felixcloutier.com/x86/pshufd
	PSHUFD
	// PXOR is the PXOR instruction https://www.felixcloutier.com/x86/pxor
	PXOR
	// PEXTRB is the PEXTRB instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq
	PEXTRB
	// PEXTRW is the PEXTRW instruction https://www.felixcloutier.com/x86/pextrw
	PEXTRW
	// PEXTRD is the PEXTRD instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq
	PEXTRD
	// PEXTRQ is the PEXTRQ instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq
	PEXTRQ
	// MOVLHPS is the MOVLHPS instruction https://www.felixcloutier.com/x86/movlhps
	MOVLHPS
	// INSERTPS is the INSERTPS instruction https://www.felixcloutier.com/x86/insertps
	INSERTPS
	// PTEST is the PTEST instruction https://www.felixcloutier.com/x86/ptest
	PTEST
	// PCMPEQB is the PCMPEQB instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd
	PCMPEQB
	// PCMPEQW is the PCMPEQW instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd
	PCMPEQW
	// PCMPEQD is the PCMPEQD instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd
	PCMPEQD
	// PCMPEQQ is the PCMPEQQ instruction https://www.felixcloutier.com/x86/pcmpeqq
	PCMPEQQ
	// PADDUSB is the PADDUSB instruction https://www.felixcloutier.com/x86/paddusb:paddusw
	PADDUSB
	// MOVSD is the MOVSD instruction https://www.felixcloutier.com/x86/movsd
	MOVSD
	// PACKSSWB is the PACKSSWB instruction https://www.felixcloutier.com/x86/packsswb:packssdw
	PACKSSWB
	// PMOVMSKB is the PMOVMSKB instruction https://www.felixcloutier.com/x86/pmovmskb
	PMOVMSKB
	// MOVMSKPS is the MOVMSKPS instruction https://www.felixcloutier.com/x86/movmskps
	MOVMSKPS
	// MOVMSKPD is the MOVMSKPD instruction https://www.felixcloutier.com/x86/movmskpd
	MOVMSKPD
	// PAND is the PAND instruction https://www.felixcloutier.com/x86/pand
	PAND
	// POR is the POR instruction https://www.felixcloutier.com/x86/por
	POR
	// PANDN is the PANDN instruction https://www.felixcloutier.com/x86/pandn
	PANDN
	// PSRAD is the PSRAD instruction https://www.felixcloutier.com/x86/psraw:psrad:psraq
	PSRAD
	// PSRAW is the PSRAW instruction https://www.felixcloutier.com/x86/psraw:psrad:psraq
	PSRAW
	// PSRLW is the PSRLW instruction https://www.felixcloutier.com/x86/psrlw:psrld:psrlq
	PSRLW
	// PSLLW is the PSLLW instruction https://www.felixcloutier.com/x86/psllw:pslld:psllq
	PSLLW
	// PUNPCKLBW is the PUNPCKLBW instruction https://www.felixcloutier.com/x86/punpcklbw:punpcklwd:punpckldq:punpcklqdq
	PUNPCKLBW
	// PUNPCKHBW is the PUNPCKHBW instruction https://www.felixcloutier.com/x86/punpckhbw:punpckhwd:punpckhdq:punpckhqdq
	PUNPCKHBW
	// CMPPS is the CMPPS instruction https://www.felixcloutier.com/x86/cmpps
	CMPPS
	// CMPPD is the https://www.felixcloutier.com/x86/cmppd
	CMPPD
	// PCMPGTQ is the PCMPGTQ instruction https://www.felixcloutier.com/x86/pcmpgtq
	PCMPGTQ
	// PCMPGTD is the PCMPGTD instruction https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd
	PCMPGTD
	// PCMPGTW is the PCMPGTW instruction https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd
	PCMPGTW
	// PCMPGTB is the PCMPGTB instruction https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd
	PCMPGTB
	// PMINSD is the PMINSD instruction https://www.felixcloutier.com/x86/pminsd:pminsq
	PMINSD
	// PMINSW is the PMINSW instruction https://www.felixcloutier.com/x86/pminsb:pminsw
	PMINSW
	// PMINSB is the PMINSB instruction https://www.felixcloutier.com/x86/pminsb:pminsw
	PMINSB
	// PMAXSD is the PMAXSD instruction https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq
	PMAXSD
	// PMAXSW is the PMAXSW instruction https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq
	PMAXSW
	// PMAXSB is the PMAXSB instruction https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq
	PMAXSB
	// PMINUD is the PMINUD instruction https://www.felixcloutier.com/x86/pminud:pminuq
	PMINUD
	// PMINUW is the PMINUW instruction https://www.felixcloutier.com/x86/pminub:pminuw
	PMINUW
	// PMINUB is the PMINUB instruction https://www.felixcloutier.com/x86/pminub:pminuw
	PMINUB
	// PMAXUD is the PMAXUD instruction https://www.felixcloutier.com/x86/pmaxud:pmaxuq
	PMAXUD
	// PMAXUW is the PMAXUW instruction https://www.felixcloutier.com/x86/pmaxub:pmaxuw
	PMAXUW
	// PMAXUB is the PMAXUB instruction https://www.felixcloutier.com/x86/pmaxub:pmaxuw
	PMAXUB
	// PMULLW is the PMULLW instruction https://www.felixcloutier.com/x86/pmullw
	PMULLW
	// PMULLD is the PMULLD instruction https://www.felixcloutier.com/x86/pmulld:pmullq
	PMULLD
	// PMULUDQ is the PMULUDQ instruction https://www.felixcloutier.com/x86/pmuludq
	PMULUDQ
	// PSUBSB is the PSUBSB instruction https://www.felixcloutier.com/x86/psubsb:psubsw
	PSUBSB
	// PSUBSW is the PSUBSW instruction https://www.felixcloutier.com/x86/psubsb:psubsw
	PSUBSW
	// PSUBUSB is the PSUBUSB instruction https://www.felixcloutier.com/x86/psubusb:psubusw
	PSUBUSB
	// PSUBUSW is the PSUBUSW instruction https://www.felixcloutier.com/x86/psubusb:psubusw
	PSUBUSW
	// PADDSW is the PADDSW instruction https://www.felixcloutier.com/x86/paddsb:paddsw
	PADDSW
	// PADDSB is the PADDSB instruction https://www.felixcloutier.com/x86/paddsb:paddsw
	PADDSB
	// PADDUSW is the PADDUSW instruction https://www.felixcloutier.com/x86/paddusb:paddusw
	PADDUSW
	// PAVGB is the PAVGB instruction https://www.felixcloutier.com/x86/pavgb:pavgw
	PAVGB
	// PAVGW is the PAVGW instruction https://www.felixcloutier.com/x86/pavgb:pavgw
	PAVGW
	// PABSB is the PABSB instruction https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq
	PABSB
	// PABSW is the PABSW instruction https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq
	PABSW
	// PABSD is the PABSD instruction https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq
	PABSD
	// BLENDVPD is the BLENDVPD instruction https://www.felixcloutier.com/x86/blendvpd
	BLENDVPD
	// MAXPD is the MAXPD instruction https://www.felixcloutier.com/x86/maxpd
	MAXPD
	// MAXPS is the MAXPS instruction https://www.felixcloutier.com/x86/maxps
	MAXPS
	// MINPD is the MINPD instruction https://www.felixcloutier.com/x86/minpd
	MINPD
	// MINPS is the MINPS instruction https://www.felixcloutier.com/x86/minps
	MINPS
	// ANDNPD is the ANDNPD instruction https://www.felixcloutier.com/x86/andnpd
	ANDNPD
	// ANDNPS is the ANDNPS instruction https://www.felixcloutier.com/x86/andnps
	ANDNPS
	// MULPS is the MULPS instruction https://www.felixcloutier.com/x86/mulps
	MULPS
	// MULPD is the MULPD instruction https://www.felixcloutier.com/x86/mulpd
	MULPD
	// DIVPS is the DIVPS instruction https://www.felixcloutier.com/x86/divps
	DIVPS
	// DIVPD is the DIVPD instruction https://www.felixcloutier.com/x86/divpd
	DIVPD
	// SQRTPS is the SQRTPS instruction https://www.felixcloutier.com/x86/sqrtps
	SQRTPS
	// SQRTPD is the SQRTPD instruction https://www.felixcloutier.com/x86/sqrtpd
	SQRTPD
	// ROUNDPS is the ROUNDPS instruction https://www.felixcloutier.com/x86/roundps
	ROUNDPS
	// ROUNDPD is the ROUNDPD instruction https://www.felixcloutier.com/x86/roundpd
	ROUNDPD
	// PALIGNR is the PALIGNR instruction https://www.felixcloutier.com/x86/palignr
	PALIGNR
	// PUNPCKLWD is the PUNPCKLWD instruction https://www.felixcloutier.com/x86/punpcklbw:punpcklwd:punpckldq:punpcklqdq
	PUNPCKLWD
	// PUNPCKHWD is the PUNPCKHWD instruction https://www.felixcloutier.com/x86/punpckhbw:punpckhwd:punpckhdq:punpckhqdq
	PUNPCKHWD
	// PMULHUW is the PMULHUW instruction https://www.felixcloutier.com/x86/pmulhuw
	PMULHUW
	// PMULDQ is the PMULDQ instruction https://www.felixcloutier.com/x86/pmuldq
	PMULDQ
	// PMULHRSW is the PMULHRSW instruction https://www.felixcloutier.com/x86/pmulhrsw
	PMULHRSW
	// PMULHW is the PMULHW instruction https://www.felixcloutier.com/x86/pmulhw
	PMULHW
	// CMPEQPS is the CMPEQPS instruction https://www.felixcloutier.com/x86/cmpps
	CMPEQPS
	// CMPEQPD is the CMPEQPD instruction https://www.felixcloutier.com/x86/cmppd
	CMPEQPD
	// CVTTPS2DQ is the CVTTPS2DQ instruction https://www.felixcloutier.com/x86/cvttps2dq
	CVTTPS2DQ
	// CVTDQ2PS is the CVTDQ2PS instruction https://www.felixcloutier.com/x86/cvtdq2ps
	CVTDQ2PS
	// MOVUPD is the MOVUPD instruction https://www.felixcloutier.com/x86/movupd
	MOVUPD
	// SHUFPS is the SHUFPS instruction https://www.felixcloutier.com/x86/shufps
	SHUFPS
	// PMADDWD is the PMADDWD instruction https://www.felixcloutier.com/x86/pmaddwd
	PMADDWD
	// CVTDQ2PD is the CVTDQ2PD instruction https://www.felixcloutier.com/x86/cvtdq2pd
	CVTDQ2PD
	// UNPCKLPS is the UNPCKLPS instruction https://www.felixcloutier.com/x86/unpcklps
	UNPCKLPS
	// PACKUSWB is the PACKUSWB instruction https://www.felixcloutier.com/x86/packuswb
	PACKUSWB
	// PACKSSDW is the PACKSSDW instruction https://www.felixcloutier.com/x86/packsswb:packssdw
	PACKSSDW
	// PACKUSDW is the PACKUSDW instruction https://www.felixcloutier.com/x86/packusdw
	PACKUSDW
	// CVTPS2PD is the CVTPS2PD instruction https://www.felixcloutier.com/x86/cvtps2pd
	CVTPS2PD
	// CVTPD2PS is the CVTPD2PS instruction https://www.felixcloutier.com/x86/cvtpd2ps
	CVTPD2PS
	// PMADDUBSW is the PMADDUBSW instruction https://www.felixcloutier.com/x86/pmaddubsw
	PMADDUBSW
	// CVTTPD2DQ is the CVTTPD2DQ instruction https://www.felixcloutier.com/x86/cvttpd2dq
	CVTTPD2DQ
)

AMD64-specific instructions.

Note: This only defines amd64 instructions used by wazero's compiler. Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm See https://www.felixcloutier.com/x86/index.html

View Source

const (
	// RegAX is the ax register
	RegAX = asm.NilRegister + 1 + iota
	// RegCX is the cx register
	RegCX
	// RegDX is the dx register
	RegDX
	// RegBX is the bx register
	RegBX
	// RegSP is the sp register
	RegSP
	// RegBP is the bp register
	RegBP
	// RegSI is the si register
	RegSI
	// RegDI is the di register
	RegDI
	// RegR8 is the r8 register
	RegR8
	// RegR9 is the r9 register
	RegR9
	// RegR10 is the r10 register
	RegR10
	// RegR11 is the r11 register
	RegR11
	// RegR12 is the r12 register
	RegR12
	// RegR13 is the r13 register
	RegR13
	// RegR14 is the r14 register
	RegR14
	// RegR15 is the r15 register
	RegR15
	// RegX0 is the x0 register
	RegX0
	// RegX1 is the x1 register
	RegX1
	// RegX2 is the x2 register
	RegX2
	// RegX3 is the x3 register
	RegX3
	// RegX4 is the x4 register
	RegX4
	// RegX5 is the x5 register
	RegX5
	// RegX6 is the x6 register
	RegX6
	// RegX7 is the x7 register
	RegX7
	// RegX8 is the x8 register
	RegX8
	// RegX9 is the x9 register
	RegX9
	// RegX10 is the x10 register
	RegX10
	// RegX11 is the x11 register
	RegX11
	// RegX12 is the x12 register
	RegX12
	// RegX13 is the x13 register
	RegX13
	// RegX14 is the x14 register
	RegX14
	// Regx15 is the x15 register
	RegX15
)

Amd64-specific registers.

Note: naming convention intentionally matches the Go assembler: https://go.dev/doc/asm See https://www.lri.fr/~filliatr/ens/compil/x86-64.pdf See https://cs.brown.edu/courses/cs033/docs/guides/x64_cheatsheet.pdf

View Source

const (
	RexPrefixNone    RexPrefix = 0x0000_0000 // Indicates that the instruction doesn't need RexPrefix.
	RexPrefixDefault RexPrefix = 0b0100_0000
	RexPrefixW                 = 0b0000_1000 | RexPrefixDefault // REX.W
	RexPrefixR                 = 0b0000_0100 | RexPrefixDefault // REX.R
	RexPrefixX                 = 0b0000_0010 | RexPrefixDefault // REX.X
	RexPrefixB                 = 0b0000_0001 | RexPrefixDefault // REX.B
)

REX prefixes are independent of each other and can be combined with OR.

Variables ¶

View Source

var RegisterToRegisterShiftOpcode = map[asm.Instruction]struct {
	opcode         []byte
	rPrefix        RexPrefix
	modRMExtension byte
}{

	ROLL: {/* contains filtered or unexported fields */},
	ROLQ: {/* contains filtered or unexported fields */},
	RORL: {/* contains filtered or unexported fields */},
	RORQ: {/* contains filtered or unexported fields */},

	SARL: {/* contains filtered or unexported fields */},
	SARQ: {/* contains filtered or unexported fields */},
	SHLL: {/* contains filtered or unexported fields */},
	SHLQ: {/* contains filtered or unexported fields */},
	SHRL: {/* contains filtered or unexported fields */},
	SHRQ: {/* contains filtered or unexported fields */},
}

Functions ¶

func FitIn32bit ¶

func FitIn32bit(v int64) bool

func InstructionName ¶

func InstructionName(instruction asm.Instruction) string

InstructionName returns the name for an instruction

func IsVectorRegister ¶

func IsVectorRegister(r asm.Register) bool

func RegisterName ¶

func RegisterName(reg asm.Register) string

RegisterName returns the name for a register

Types ¶

type Assembler ¶

type Assembler interface {
	asm.AssemblerBase

	// CompileJumpToMemory adds jump-type instruction whose destination is stored in the memory address specified by `baseReg+offset`,
	// and returns the corresponding Node in the assembled linked list.
	CompileJumpToMemory(jmpInstruction asm.Instruction, baseReg asm.Register, offset asm.ConstantValue)

	// CompileRegisterToRegisterWithArg adds an instruction where source and destination
	// are `from` and `to` registers.
	CompileRegisterToRegisterWithArg(instruction asm.Instruction, from, to asm.Register, arg byte)

	// CompileMemoryWithIndexToRegister adds an instruction where source operand is the memory address
	// specified as `srcBaseReg + srcOffsetConst + srcIndex*srcScale` and destination is the register `dstReg`.
	// Note: sourceScale must be one of 1, 2, 4, 8.
	CompileMemoryWithIndexToRegister(
		instruction asm.Instruction,
		srcBaseReg asm.Register,
		srcOffsetConst int64,
		srcIndex asm.Register,
		srcScale int16,
		dstReg asm.Register,
	)

	// CompileMemoryWithIndexAndArgToRegister is the same as CompileMemoryWithIndexToRegister except that this
	// also accepts one argument.
	CompileMemoryWithIndexAndArgToRegister(
		instruction asm.Instruction,
		srcBaseReg asm.Register,
		srcOffsetConst int64,
		srcIndex asm.Register,
		srcScale int16,
		dstReg asm.Register,
		arg byte,
	)

	// CompileRegisterToMemoryWithIndex adds an instruction where source operand is the register `srcReg`,
	// and the destination is the memory address specified as `dstBaseReg + dstOffsetConst + dstIndex*dstScale`
	// Note: dstScale must be one of 1, 2, 4, 8.
	CompileRegisterToMemoryWithIndex(
		instruction asm.Instruction,
		srcReg asm.Register,
		dstBaseReg asm.Register,
		dstOffsetConst int64,
		dstIndex asm.Register,
		dstScale int16,
	)

	// CompileRegisterToMemoryWithIndexAndArg is the same as CompileRegisterToMemoryWithIndex except that this
	// also accepts one argument.
	CompileRegisterToMemoryWithIndexAndArg(
		instruction asm.Instruction,
		srcReg asm.Register,
		dstBaseReg asm.Register,
		dstOffsetConst int64,
		dstIndex asm.Register,
		dstScale int16,
		arg byte,
	)

	// CompileRegisterToConst adds an instruction where source operand is the register `srcRegister`,
	// and the destination is the const `value`.
	CompileRegisterToConst(instruction asm.Instruction, srcRegister asm.Register, value int64) asm.Node

	// CompileRegisterToNone adds an instruction where source operand is the register `register`,
	// and there's no destination operand.
	CompileRegisterToNone(instruction asm.Instruction, register asm.Register)

	// CompileNoneToRegister adds an instruction where destination operand is the register `register`,
	// and there's no source operand.
	CompileNoneToRegister(instruction asm.Instruction, register asm.Register)

	// CompileNoneToMemory adds an instruction where destination operand is the memory address specified
	// as `baseReg+offset`. and there's no source operand.
	CompileNoneToMemory(instruction asm.Instruction, baseReg asm.Register, offset int64)

	// CompileConstToMemory adds an instruction where source operand is the constant `value` and
	// the destination is the memory address specified as `dstBaseReg+dstOffset`.
	CompileConstToMemory(instruction asm.Instruction, value int64, dstBaseReg asm.Register, dstOffset int64) asm.Node

	// CompileMemoryToConst adds an instruction where source operand is the memory address, and
	// the destination is the constant `value`.
	CompileMemoryToConst(instruction asm.Instruction, srcBaseReg asm.Register, srcOffset int64, value int64) asm.Node

	// CompileStaticConstToRegister adds an instruction where the source operand is asm.StaticConst located in the
	// memory and the destination is the dstReg.
	CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register) error

	// CompileRegisterToStaticConst adds an instruction where the destination operand is asm.StaticConst located in the
	// memory and the source is the srcReg.
	CompileRegisterToStaticConst(instruction asm.Instruction, srcReg asm.Register, c *asm.StaticConst) error
}

Assembler is the interface used by amd64 compiler.

type AssemblerImpl ¶

type AssemblerImpl struct {
	asm.BaseAssemblerImpl

	// MaxDisplacementForConstantPool is fixed to defaultMaxDisplacementForConstantPool
	// but have it as an exported field here for testability.
	MaxDisplacementForConstantPool int
	// contains filtered or unexported fields
}

AssemblerImpl implements Assembler.

func NewAssembler ¶

func NewAssembler() *AssemblerImpl

func (*AssemblerImpl) Assemble ¶

func (a *AssemblerImpl) Assemble() ([]byte, error)

Assemble implements asm.AssemblerBase

func (*AssemblerImpl) CompileConstToMemory ¶

func (a *AssemblerImpl) CompileConstToMemory(
	instruction asm.Instruction,
	value asm.ConstantValue,
	dstbaseReg asm.Register,
	dstOffset asm.ConstantValue,
) asm.Node

CompileConstToMemory implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileConstToRegister ¶

func (a *AssemblerImpl) CompileConstToRegister(
	instruction asm.Instruction,
	value asm.ConstantValue,
	destinationReg asm.Register,
) (inst asm.Node)

CompileConstToRegister implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileJump ¶

func (a *AssemblerImpl) CompileJump(jmpInstruction asm.Instruction) asm.Node

CompileJump implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileJumpToMemory ¶

func (a *AssemblerImpl) CompileJumpToMemory(
	jmpInstruction asm.Instruction,
	baseReg asm.Register,
	offset asm.ConstantValue,
)

CompileJumpToMemory implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileJumpToRegister ¶

func (a *AssemblerImpl) CompileJumpToRegister(jmpInstruction asm.Instruction, reg asm.Register)

CompileJumpToRegister implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileMemoryToConst ¶

func (a *AssemblerImpl) CompileMemoryToConst(
	instruction asm.Instruction,
	srcBaseReg asm.Register,
	srcOffset, value asm.ConstantValue,
) asm.Node

CompileMemoryToConst implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileMemoryToRegister ¶

func (a *AssemblerImpl) CompileMemoryToRegister(
	instruction asm.Instruction,
	sourceBaseReg asm.Register,
	sourceOffsetConst asm.ConstantValue,
	destinationReg asm.Register,
)

CompileMemoryToRegister implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileMemoryWithIndexAndArgToRegister ¶

func (a *AssemblerImpl) CompileMemoryWithIndexAndArgToRegister(
	instruction asm.Instruction,
	srcBaseReg asm.Register,
	srcOffsetConst asm.ConstantValue,
	srcIndex asm.Register,
	srcScale int16,
	dstReg asm.Register,
	arg byte,
)

CompileMemoryWithIndexAndArgToRegister implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileMemoryWithIndexToRegister ¶

func (a *AssemblerImpl) CompileMemoryWithIndexToRegister(
	instruction asm.Instruction,
	srcBaseReg asm.Register,
	srcOffsetConst asm.ConstantValue,
	srcIndex asm.Register,
	srcScale int16,
	dstReg asm.Register,
)

CompileMemoryWithIndexToRegister implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileNoneToMemory ¶

func (a *AssemblerImpl) CompileNoneToMemory(
	instruction asm.Instruction,
	baseReg asm.Register,
	offset asm.ConstantValue,
)

CompileNoneToMemory implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileNoneToRegister ¶

func (a *AssemblerImpl) CompileNoneToRegister(instruction asm.Instruction, register asm.Register)

CompileNoneToRegister implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileReadInstructionAddress ¶

func (a *AssemblerImpl) CompileReadInstructionAddress(
	destinationRegister asm.Register,
	beforeAcquisitionTargetInstruction asm.Instruction,
)

CompileReadInstructionAddress implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileRegisterToConst ¶

func (a *AssemblerImpl) CompileRegisterToConst(
	instruction asm.Instruction,
	srcRegister asm.Register,
	value asm.ConstantValue,
) asm.Node

CompileRegisterToConst implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileRegisterToMemory ¶

func (a *AssemblerImpl) CompileRegisterToMemory(
	instruction asm.Instruction,
	sourceRegister, destinationBaseRegister asm.Register,
	destinationOffsetConst asm.ConstantValue,
)

CompileRegisterToMemory implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileRegisterToMemoryWithIndex ¶

func (a *AssemblerImpl) CompileRegisterToMemoryWithIndex(
	instruction asm.Instruction,
	srcReg, dstBaseReg asm.Register,
	dstOffsetConst asm.ConstantValue,
	dstIndex asm.Register,
	dstScale int16,
)

CompileRegisterToMemoryWithIndex implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileRegisterToMemoryWithIndexAndArg ¶

func (a *AssemblerImpl) CompileRegisterToMemoryWithIndexAndArg(
	instruction asm.Instruction,
	srcReg, dstBaseReg asm.Register,
	dstOffsetConst asm.ConstantValue,
	dstIndex asm.Register,
	dstScale int16,
	arg byte,
)

CompileRegisterToMemoryWithIndexAndArg implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileRegisterToNone ¶

func (a *AssemblerImpl) CompileRegisterToNone(instruction asm.Instruction, register asm.Register)

CompileRegisterToNone implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileRegisterToRegister ¶

func (a *AssemblerImpl) CompileRegisterToRegister(instruction asm.Instruction, from, to asm.Register)

CompileRegisterToRegister implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileRegisterToRegisterWithArg ¶

func (a *AssemblerImpl) CompileRegisterToRegisterWithArg(
	instruction asm.Instruction,
	from, to asm.Register,
	arg byte,
)

CompileRegisterToRegisterWithArg implements the same method as documented on amd64.Assembler.

func (*AssemblerImpl) CompileRegisterToStaticConst ¶

func (a *AssemblerImpl) CompileRegisterToStaticConst(instruction asm.Instruction, srcReg asm.Register, c *asm.StaticConst) (err error)

CompileRegisterToStaticConst implements Assembler.CompileRegisterToStaticConst.

func (*AssemblerImpl) CompileStandAlone ¶

func (a *AssemblerImpl) CompileStandAlone(instruction asm.Instruction) asm.Node

CompileStandAlone implements the same method as documented on asm.AssemblerBase.

func (*AssemblerImpl) CompileStaticConstToRegister ¶

func (a *AssemblerImpl) CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register) (err error)

CompileStaticConstToRegister implements Assembler.CompileStaticConstToRegister.

func (*AssemblerImpl) Encode ¶

func (a *AssemblerImpl) Encode() (err error)

func (*AssemblerImpl) EncodeNode ¶

func (a *AssemblerImpl) EncodeNode(n *nodeImpl) (err error)

EncodeNode encodes the given node into writer.

func (*AssemblerImpl) InitializeNodesForEncoding ¶

func (a *AssemblerImpl) InitializeNodesForEncoding()

InitializeNodesForEncoding initializes nodeImpl.flag and determine all the jumps are forward or backward jump.

func (*AssemblerImpl) ResolveForwardRelativeJumps ¶

func (a *AssemblerImpl) ResolveForwardRelativeJumps(target *nodeImpl) (err error)

func (*AssemblerImpl) WriteConst ¶

func (a *AssemblerImpl) WriteConst(v int64, length byte)

type RexPrefix ¶

type RexPrefix = byte

RexPrefix represents REX prefix https://wiki.osdev.org/X86-64_Instruction_Encoding#REX_prefix

Source Files ¶

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