in

package
v0.15.1 Latest Latest
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 Go to latest Published: Feb 2, 2019 License: BSD-3-Clause Imports: 3 Imported by: 0

Documentation

Index

Constants

View Source 
const (
	EQ = Cond(0x0) // equal to
	NE = Cond(0x1) // not equal to
	CS = Cond(0x2) // carry set
	CC = Cond(0x3) // carry clear
	MI = Cond(0x4) // minus, negative
	PL = Cond(0x5) // positive or zero
	VS = Cond(0x6) // signed overflow
	VC = Cond(0x7) // no signed overflow
	HI = Cond(0x8) // greater than (unsigned)
	LS = Cond(0x9) // less than or equal to (unsigned)
	GE = Cond(0xa) // greater than or equal to (signed)
	LT = Cond(0xb) // less than (signed)
	GT = Cond(0xc) // greater than (signed)
	LE = Cond(0xd) // less than or equal to (signed)

	HS = CS // greater than or equal to (unsigned)
	LO = CC // less than (unsigned)
)
View Source 
const (
	UXTB = Ext(0 << 13)
	UXTH = Ext(1 << 13)
	UXTW = Ext(2 << 13)
	UXTX = Ext(3 << 13)
	SXTB = Ext(4 << 13)
	SXTH = Ext(5 << 13)
	SXTW = Ext(6 << 13)
	SXTX = Ext(7 << 13)
)
View Source 
const (
	// Compare & branch (immediate)
	CBZ  = RegImm19Size(0x1a<<25 | 0<<24)
	CBNZ = RegImm19Size(0x1a<<25 | 1<<24)

	// Conditional branch (immediate)
	Bc = CondImm19(0x2a<<25 | 0<<24 | 0<<4)

	// Exception generation
	BRK = Imm16(0xd4<<24 | 1<<21 | 0<<2 | 0<<0)
	HLT = Imm16(0xd4<<24 | 2<<21 | 0<<2 | 0<<0)

	// Test & branch (immediate)
	TBZ  = RegImm14Bit(0x1b<<25 | 0<<24)
	TBNZ = RegImm14Bit(0x1b<<25 | 1<<24)

	// Unconditional branch (immediate)
	B  = Imm26(0<<31 | 5<<26)
	BL = Imm26(1<<31 | 5<<26)

	// Unconditional branch (register)
	BR  = Reg(0x6b<<25 | 0<<21 | 0x1f<<16 | 0<<10 | 0<<0)
	BLR = Reg(0x6b<<25 | 1<<21 | 0x1f<<16 | 0<<10 | 0<<0)
	RET = Reg(0x6b<<25 | 2<<21 | 0x1f<<16 | 0<<10 | 0<<0)

	// Load/store register (immediate post-indexed)
	STRpost = RegRegImm9Size(1<<31 | 7<<27 | 0<<26 | 0<<24 | 0<<22 | 0<<21 | 1<<10)
	LDRpost = RegRegImm9Size(1<<31 | 7<<27 | 0<<26 | 0<<24 | 1<<22 | 0<<21 | 1<<10)

	// Load/store register (immediate pre-indexed)
	STRpre = RegRegImm9Size(1<<31 | 7<<27 | 0<<26 | 0<<24 | 0<<22 | 0<<21 | 3<<10)
	LDRpre = RegRegImm9Size(1<<31 | 7<<27 | 0<<26 | 0<<24 | 1<<22 | 0<<21 | 3<<10)

	// Load/store register (register offset)
	STRr = RegRegSOptionRegSize(1<<31 | 7<<27 | 0<<26 | 0<<24 | 0<<22 | 1<<21 | 2<<10)
	LDRr = RegRegSOptionRegSize(1<<31 | 7<<27 | 0<<26 | 0<<24 | 1<<22 | 1<<21 | 2<<10)

	// Load/store register (unscaled immediate)
	STUR = RegRegImm9Size(1<<31 | 7<<27 | 0<<26 | 0<<24 | 0<<22 | 0<<21 | 0<<10)
	LDUR = RegRegImm9Size(1<<31 | 7<<27 | 0<<26 | 0<<24 | 1<<22 | 0<<21 | 0<<10)

	// Load/store register (unsigned immediate)
	STR = RegRegImm12Size(1<<31 | 7<<27 | 0<<26 | 1<<24 | 0<<22)
	LDR = RegRegImm12Size(1<<31 | 7<<27 | 0<<26 | 1<<24 | 1<<22)

	// Add/subtract (immediate)
	ADDi  = RegRegImm12ShiftSf(0<<30 | 0<<29 | 0x11<<24)
	ADDSi = RegRegImm12ShiftSf(0<<30 | 1<<29 | 0x11<<24)
	SUBi  = RegRegImm12ShiftSf(1<<30 | 0<<29 | 0x11<<24)
	SUBSi = RegRegImm12ShiftSf(1<<30 | 1<<29 | 0x11<<24)

	// Bitfield
	SBFM = RegRegImm6Imm6NSf(0<<29 | 0x26<<23 | 0<<22)
	BFM  = RegRegImm6Imm6NSf(1<<29 | 0x26<<23 | 0<<22)
	UBFM = RegRegImm6Imm6NSf(2<<29 | 0x26<<23 | 0<<22)

	// Extract
	EXTR = RegRegImm6RegNSf(0<<29 | 0x27<<23 | 0<<21)

	// Logical (immediate)
	ANDi  = RegRegImm6Imm6NSf(0<<29 | 0x24<<23)
	ORRi  = RegRegImm6Imm6NSf(1<<29 | 0x24<<23)
	EORi  = RegRegImm6Imm6NSf(2<<29 | 0x24<<23)
	ANDSi = RegRegImm6Imm6NSf(3<<29 | 0x24<<23)

	// Move wide (immediate)
	MOVN = RegImm16HwSf(0<<29 | 0x25<<23)
	MOVZ = RegImm16HwSf(2<<29 | 0x25<<23)
	MOVK = RegImm16HwSf(3<<29 | 0x25<<23)

	// Address generation
	ADR  = RegImm19Imm2(0<<31 | 0x10<<24)
	ADRP = RegImm19Imm2(1<<31 | 0x10<<24)

	// Add/subtract (extended register)
	ADDe  = RegRegImm3ExtRegSf(0<<30 | 0<<29 | 0x0b<<24 | 0<<22 | 1<<21)
	ADDSe = RegRegImm3ExtRegSf(0<<30 | 1<<29 | 0x0b<<24 | 0<<22 | 1<<21)
	SUBe  = RegRegImm3ExtRegSf(1<<30 | 0<<29 | 0x0b<<24 | 0<<22 | 1<<21)
	SUBSe = RegRegImm3ExtRegSf(1<<30 | 1<<29 | 0x0b<<24 | 0<<22 | 1<<21)

	// Add/subtract (shifted register)
	ADDs  = RegRegImm6RegShiftSf(0<<30 | 0<<29 | 0x0b<<24 | 0<<21)
	ADDSs = RegRegImm6RegShiftSf(0<<30 | 1<<29 | 0x0b<<24 | 0<<21)
	SUBs  = RegRegImm6RegShiftSf(1<<30 | 0<<29 | 0x0b<<24 | 0<<21)
	SUBSs = RegRegImm6RegShiftSf(1<<30 | 1<<29 | 0x0b<<24 | 0<<21)

	// Conditional select
	CSEL  = RegRegCondRegSf(0<<30 | 0<<29 | 0xd4<<21 | 0<<10)
	CSINC = RegRegCondRegSf(0<<30 | 0<<29 | 0xd4<<21 | 1<<10)
	CSINV = RegRegCondRegSf(0<<30 | 1<<29 | 0xd4<<21 | 0<<10)
	CSNEG = RegRegCondRegSf(0<<30 | 1<<29 | 0xd4<<21 | 1<<10)

	// Logical (shifted register)
	ANDs  = RegRegImm6RegShiftSf(0<<29 | 0x0a<<24 | 0<<21)
	BIC   = RegRegImm6RegShiftSf(0<<29 | 0x0a<<24 | 1<<21)
	ORRs  = RegRegImm6RegShiftSf(1<<29 | 0x0a<<24 | 0<<21)
	ORN   = RegRegImm6RegShiftSf(1<<29 | 0x0a<<24 | 1<<21)
	EORs  = RegRegImm6RegShiftSf(2<<29 | 0x0a<<24 | 0<<21)
	EON   = RegRegImm6RegShiftSf(2<<29 | 0x0a<<24 | 1<<21)
	ANDSs = RegRegImm6RegShiftSf(3<<29 | 0x0a<<24 | 0<<21)
	BICS  = RegRegImm6RegShiftSf(3<<29 | 0x0a<<24 | 1<<21)
)
View Source 
const (
	AddsubAdd = Addsub(0)
	AddsubSub = Addsub(1)
)
View Source 
const (
	LogicAnd = Logic(0)
	LogicOrr = Logic(1)
	LogicEor = Logic(2)
)
View Source 
const (
	StoreB   = Memory(0<<14 | 7<<11 | 0<<10 | 0<<8 | 0<<6 | 0)
	LoadB    = Memory(0<<14 | 7<<11 | 0<<10 | 0<<8 | 1<<6 | 0)
	LoadSB64 = Memory(0<<14 | 7<<11 | 0<<10 | 0<<8 | 2<<6 | 0)
	LoadSB32 = Memory(0<<14 | 7<<11 | 0<<10 | 0<<8 | 3<<6 | 0)
	StoreH   = Memory(1<<14 | 7<<11 | 0<<10 | 0<<8 | 0<<6 | 1)
	LoadH    = Memory(1<<14 | 7<<11 | 0<<10 | 0<<8 | 1<<6 | 1)
	LoadSH64 = Memory(1<<14 | 7<<11 | 0<<10 | 0<<8 | 2<<6 | 1)
	LoadSH32 = Memory(1<<14 | 7<<11 | 0<<10 | 0<<8 | 3<<6 | 1)
	StoreW   = Memory(2<<14 | 7<<11 | 0<<10 | 0<<8 | 0<<6 | 3)
	LoadW    = Memory(2<<14 | 7<<11 | 0<<10 | 0<<8 | 1<<6 | 3)
	LoadSW64 = Memory(2<<14 | 7<<11 | 0<<10 | 0<<8 | 2<<6 | 3)
	StoreD   = Memory(3<<14 | 7<<11 | 0<<10 | 0<<8 | 0<<6 | 7)
	LoadD    = Memory(3<<14 | 7<<11 | 0<<10 | 0<<8 | 1<<6 | 7)
)
View Source 
const (
	RegFakeSP = reg.R(29)
)

Variables

This section is empty.

Functions

func Int12 

func Int12(i int32) uint32

func Int14 

func Int14(i int32) uint32

func Int16 

func Int16(i int64) uint32

func Int19 

func Int19(i int32) uint32

func Int26 

func Int26(i int32) uint32

func Int9 

func Int9(i int32) uint32

func LSL 

func LSL(rd, rn reg.R, uimm uint32, t wa.Type) uint32

func PopIntReg 

func PopIntReg(r reg.R) uint32

func PushIntReg 

func PushIntReg(r reg.R) uint32

func Uint12 

func Uint12(i uint64) uint32

func Uint16 

func Uint16(i uint64) uint32

Types

type Addsub 

type Addsub uint8

Add/subtract instruction's "op" field

func (Addsub) OpcodeImm 

func (op Addsub) OpcodeImm() RegRegImm12ShiftSf

func (Addsub) OpcodeRegExt 

func (op Addsub) OpcodeRegExt() RegRegImm3ExtRegSf

type Cond 

type Cond uint32

type CondImm19 

type CondImm19 uint32

func (CondImm19) CondI19 

func (op CondImm19) CondI19(cond Cond, imm uint32) uint32

type Ext 

type Ext uint32

func SizeSignExt 

func SizeSignExt(t wa.Type) Ext

func SizeZeroExt 

func SizeZeroExt(t wa.Type) Ext

type Imm16 

type Imm16 uint32

func (Imm16) I16 

func (op Imm16) I16(imm uint32) uint32

type Imm26 

type Imm26 uint32

func (Imm26) I26 

func (op Imm26) I26(imm uint32) uint32

type Logic 

type Logic uint8

Logical instruction's "opc" field

func (Logic) OpcodeImm 

func (op Logic) OpcodeImm() RegRegImm6Imm6NSf

func (Logic) OpcodeReg 

func (op Logic) OpcodeReg() RegRegImm6RegShiftSf

type Memory 

type Memory uint16

Load/store instruction's most significant half-word | access size in bytes minus one

func (Memory) OpcodeUnscaled 

func (op Memory) OpcodeUnscaled() RegRegImm9

func (Memory) SizeReach 

func (op Memory) SizeReach() uint64

type Reg 

type Reg uint32

func (Reg) Rn 

func (op Reg) Rn(rn reg.R) uint32

type RegImm14Bit 

type RegImm14Bit uint32

func (RegImm14Bit) RtI14Bit 

func (op RegImm14Bit) RtI14Bit(rt reg.R, imm, bit uint32) uint32

type RegImm16HwSf 

type RegImm16HwSf uint32

func (RegImm16HwSf) RdI16Hw 

func (op RegImm16HwSf) RdI16Hw(rd reg.R, imm, hw uint32, t wa.Type) uint32

type RegImm19Imm2 

type RegImm19Imm2 uint32

func (RegImm19Imm2) RdI19hiI2lo 

func (op RegImm19Imm2) RdI19hiI2lo(r reg.R, hi, lo uint32) uint32

type RegImm19Size 

type RegImm19Size uint32

func (RegImm19Size) RtI19 

func (op RegImm19Size) RtI19(r reg.R, imm uint32, t wa.Type) uint32

type RegRegCondRegSf 

type RegRegCondRegSf uint32

func (RegRegCondRegSf) RdRnCondRm 

func (op RegRegCondRegSf) RdRnCondRm(rd, rn reg.R, cond Cond, rm reg.R, t wa.Type) uint32

type RegRegImm12ShiftSf 

type RegRegImm12ShiftSf uint32

func (RegRegImm12ShiftSf) RdRnI12S2 

func (op RegRegImm12ShiftSf) RdRnI12S2(rd, rn reg.R, imm, shift uint32, t wa.Type) uint32

type RegRegImm12Size 

type RegRegImm12Size uint32

func (RegRegImm12Size) RdRnI12 

func (op RegRegImm12Size) RdRnI12(rt, rn reg.R, imm uint32, t wa.Type) uint32

type RegRegImm3ExtRegSf 

type RegRegImm3ExtRegSf uint32

func (RegRegImm3ExtRegSf) RdRnI3ExtRm 

func (op RegRegImm3ExtRegSf) RdRnI3ExtRm(rd, rn reg.R, imm uint32, option Ext, rm reg.R, t wa.Type) uint32

type RegRegImm6Imm6NSf 

type RegRegImm6Imm6NSf uint32

func (RegRegImm6Imm6NSf) RdRnI6sI6r 

func (op RegRegImm6Imm6NSf) RdRnI6sI6r(rd, rn reg.R, imms, immr uint32, t wa.Type) uint32

type RegRegImm6RegNSf 

type RegRegImm6RegNSf uint32

func (RegRegImm6RegNSf) RdRnI6Rm 

func (op RegRegImm6RegNSf) RdRnI6Rm(rd, rn reg.R, imm uint32, rm reg.R, t wa.Type) uint32

type RegRegImm6RegShiftSf 

type RegRegImm6RegShiftSf uint32

func (RegRegImm6RegShiftSf) RdRnI6RmS2 

func (op RegRegImm6RegShiftSf) RdRnI6RmS2(rd, rn reg.R, imm uint32, rm reg.R, shift uint32, t wa.Type) uint32

type RegRegImm9 

type RegRegImm9 uint32

func (RegRegImm9) RtRnI9 

func (op RegRegImm9) RtRnI9(rt, rn reg.R, imm uint32) uint32

type RegRegImm9Size 

type RegRegImm9Size uint32

func (RegRegImm9Size) RtRnI9 

func (op RegRegImm9Size) RtRnI9(rt, rn reg.R, imm uint32, t wa.Type) uint32

type RegRegSOptionRegSize 

type RegRegSOptionRegSize uint32

func (RegRegSOptionRegSize) RtRnSOptionRm 

func (op RegRegSOptionRegSize) RtRnSOptionRm(rt, rn reg.R, s, option uint32, rm reg.R, t wa.Type) uint32

Source Files

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