protocol

Documentation

Overview

Package protocol defines the communication between components.

Index

• Constants
• type CSRCmd
• type CSRDecodeIO
• type ExecCommit
• type ExecRsp
• type ExecRspType
• type Exit
• type ExtensionConfig
• type FetchJmp
• type FetchRsp
• type FetchRspType
• type FunctionalUnit
• type IssueUnit
• type LoadRes
• type MStatus
• type MemCmd
• type MemRead
• type MemRsp
• type MemRspType
• type MemWrite
• type Printf
• type RegType
• type UOpcode
• type Uop
• type Width
• type XcptCause

Constants

const MemTransLen uint64 = 16

MemTransLen is the byte length of a single read or write transaction.

Types

type CSRCmd

type CSRCmd uint8

const (
	CSRN CSRCmd = 0
)

type CSRDecodeIO

type CSRDecodeIO struct {
	CSR           uint64
	FPIllegal     bool
	VectorIllegal bool
	FPCSR         bool
	RoccIllegal   bool
	ReadIllegal   bool
	WriteIllegal  bool
	WriteFlush    bool
	SystemIllegal bool
}

CSRDecodeIO represents direct communication between the CSR and Decode stage. From: rocket-chip/src/main/scala/rocket/CSR.scala

type ExecCommit

type ExecCommit struct {
	InsnWord uint32
	PC       uint64
}

ExecCommit contains info for the exec stage to commit state.

type ExecRsp

type ExecRsp struct {
	Type  ExecRspType
	Read  MemRead
	Write MemWrite
	Jmp   FetchJmp
	// AMO   AMOOp
	LR    LoadRes
	Print Printf
	Exit  Exit
}

ExecRsp is emitted by the exec stage and inspected by other modules in the pipeline.

type ExecRspType

type ExecRspType uint16

ExecRspType enumerates the type of Exec stage response.

const (
	// EmptyExecRsp indicates no response.
	EmptyExecRsp ExecRspType = iota
	// JmpPCRsp indicates the response contains a new target PC.
	JmpPCRsp
	// ExecMemWrite indicates the response delivers data to the memory module.
	ExecMemWrite
	// ExecMemRead indicates the exec stage needs to read from memory.
	ExecMemRead
	// AMORsp indicates that the memory unit should execute an atomic operation.
	AMORsp
	// LRRsp indicates that the memory unit should commit a load reservation.
	LRRsp
	// SCRsp indicates that the memory unit should attempt a store conditional
	// operation.
	SCRsp
	// PrintfRsp indicates that the memory unit should read bytes and the exec
	// stage should print those bytes to stdout.
	PrintfRsp
	// ExitRsp indicates that the controller should cease execution.
	ExitRsp
)

type Exit

type Exit struct {
	Code int
}

type ExtensionConfig

type ExtensionConfig uint16

ExtensionConfig is a bitmask for configuring which risc-v extensions to use in initialization.

const (
	ExtM ExtensionConfig = 1 << 0
	ExtA ExtensionConfig = 1 << 1
	ExtF ExtensionConfig = 1 << 2
	ExtD ExtensionConfig = 1 << 3
	ExtC ExtensionConfig = 1 << 4
)

RISC-V extension options, these will automatically be the correct version for 32 or 64 bit

type FetchJmp

type FetchJmp struct {
	PC uint64
}

FetchJmp contains the jump PC from which the module should retrieve the next instruction bits.

type FetchRsp

type FetchRsp struct {
	Type   FetchRspType
	Read   MemRead
	Commit ExecCommit
}

FetchRsp contains response messages from the fetch stage.

type FetchRspType

type FetchRspType byte

FetchRspType indicates the type of fetch response.

const (
	// EmptyFetchRsp indicates that no response is available.
	EmptyFetchRsp FetchRspType = iota
	// FetchMemRead indicates that the fetch stage must read from higher level memory.
	FetchMemRead
	// FetchCommit indicates that the fetch stage is emitting valid isntruction bits.
	FetchCommit
)

type FunctionalUnit

type FunctionalUnit uint16

const (
	FUALU    FunctionalUnit = 1 << 0
	FUJmp    FunctionalUnit = 1 << 1
	FUMem    FunctionalUnit = 1 << 2
	FUMul    FunctionalUnit = 1 << 3
	FUDiv    FunctionalUnit = 1 << 4
	FUCSR    FunctionalUnit = 1 << 5
	FUFPU    FunctionalUnit = 1 << 6
	FUFDV    FunctionalUnit = 1 << 7
	FUI2F    FunctionalUnit = 1 << 8
	FUF2I    FunctionalUnit = 1 << 9
	FUF2IMem FunctionalUnit = FUF2I & FUMem
)

type IssueUnit

type IssueUnit uint8

const (
	IUInt IssueUnit = iota
	IULSU
	IUFloat
)

type LoadRes

type LoadRes struct {
	Addr   uint64
	Len    uint64
	HartID uint64
}

LoadRes contains information for a load reservation operation.

type MStatus

type MStatus struct {
	// not truly part of mstatus, but convenient
	Debug bool
	Cease bool
	WFI   bool
	ISA   ExtensionConfig

	DPrv   uint8 // effective privilege for data accesses
	Prv    uint8 // not truly part of mstatus, but convenient
	SU     bool
	Zero2  uint32
	SXl    uint8
	UXl    uint8
	SDRV32 bool
	Zero1  uint8
	TSR    bool
	TW     bool
	TVM    bool
	MXR    bool
	Sum    bool
	MPrv   bool
	XS     uint8
	FS     uint8
	MPP    uint8
	VS     uint8
	SPP    bool
	MPIE   bool
	HPIE   bool
	SPIE   bool
	UPIE   bool
	MIE    bool
	HIE    bool
	SIE    bool
	UIE    bool
}

MStatus represents the MStatus output from a CSR stage. From: rocket-chip/src/main/scala/rocket/CSR.scala

type MemCmd

type MemCmd uint32

const (
	MXRD MemCmd = iota
	MXWR
	MPFR
	MPFW
	MXASWAP
	MFLUSHALL
	MXLR
	MXSC
	MXAADD
	MXAXOR
	MXAOR
	MXAAND
	MXAMIN
	MXAMAX
	MXAMINU
	MXAMAXU
	MFLUSH
	MPWR
	MPRODUCE
	MCLEAN
	MSFENCE
	MWOK
)

type MemRead

type MemRead struct {
	Addr uint64
	Len  uint64
}

MemRead contains info for a memory read operation.

type MemRsp

type MemRsp struct {
	Type MemRspType
	// TODO: Get rid of dynamic structure.
	Data []byte
}

MemRsp contains fields for all memory response types.

type MemRspType

type MemRspType byte

MemRspType enumerates the types of responses made by the memory module.

const (
	// InvalidMemRsp indicates a bad response.
	InvalidMemRsp MemRspType = iota
	// EmptyMemRsp indicates no response.
	EmptyMemRsp
	// MemReadRsp indicates that the memory module is responding with data.
	MemReadRsp
)

type MemWrite

type MemWrite struct {
	Addr uint64
	Len  uint64
	Data [8]byte
}

MemWrite contains info for a memory write.

type Printf

type Printf struct {
	Addr uint64
	Len  uint64
}

Printf contains information needed to service a Printf call.

type RegType

type RegType uint8

const (
	RTNone RegType = iota
	RTFix
	RTFloat
	RTPass
)

type UOpcode

type UOpcode uint8

const (
	UopNOP UOpcode = iota
	UopLD
	UopSTA // store address generation
	UopSTD // store data generation
	UopLUI

	UopADDI
	UopANDI
	UopORI
	UopXORI
	UopSLTI
	UopSLTIU
	UopSLLI
	UopSRAI
	UopSRLI

	UopSLL
	UopADD
	UopSUB
	UopSLT
	UopSLTU
	UopAND
	UopOR
	UopXOR
	UopSRA
	UopSRL

	UopBEQ
	UopBNE
	UopBGE
	UopBGEU
	UopBLT
	UopBLTU
	UopCSRRW
	UopCSRRS
	UopCSRRC
	UopCSRRWI
	UopCSRRSI
	UopCSRRCI

	UopJ
	UopJAL
	UopJALR
	UopAUIPC

	UopCFLSH
	UopFENCE

	UopADDIW
	UopADDW
	UopSUBW
	UopSLLIW
	UopSLLW
	UopSRAIW
	UopSRAW
	UopSRLIW
	UopSRLW
	UopMUL
	UopMULH
	UopMULHU
	UopMULHS
	UopMULW
	UopDIV
	UopDIVU
	UopREM
	UopREMU
	UopDIVW
	UopDIVUW
	UopREMW
	UopREMUW

	UopFENCEI

	UopAMOAG // AMO-address gen (use normal STD for datagen)

	UopFMVSX
	UopFMVDX
	UopFMVXS
	UopFMVXD

	UopFSGNJS
	UopFSGNJD

	UopFCVTSD
	UopFCVTDS

	UopFCVTSX
	UopFCVTDX

	UopFCVTXS
	UopFCVTXD

	UopCMPRS
	UopCMPRD

	UopFCLASSS
	UopFCLASSD

	UopFMINMAXS
	UopFMINMAXD

	UopFADDS
	UopFSUBS
	UopFMULS
	UopFADDD
	UopFSUBD
	UopFMULD

	UopFMADDS
	UopFMSUBS
	UopFNMADDS
	UopFNMSUBS
	UopFMADDD
	UopFMSUBD
	UopFNMADDD
	UopFNMSUBD

	UopFDIVS
	UopFDIVD
	UopFSQRTS
	UopFSQRTD

	UopWFI  // pass uop down the CSR pipeline
	UopERET // pass uop down the CSR pipeline, also is ERET
	UopSFENCE

	UopROCC

	UopMOV // conditional mov decoded from "add rd, x0, rs2"
)

type Uop

type Uop struct {
	UOpcode       UOpcode
	InsnWord      uint32
	DebugInsnWord uint32
	IsRVC         bool
	DebugPC       uint64
	Iss           IssueUnit
	Func          FunctionalUnit

	IssueWindow uint8
	IWP1Poison  bool
	IWP2Poison  bool

	IsBranch bool
	IsJalr   bool
	IsJal    bool
	IsSFB    bool

	BranchMask uint8
	BranchTag  uint8

	FTQIdx    uint8
	EdgeInsn  bool
	PCLowBits uint8

	BranchTaken bool
	ImmPacked   uint64

	CSRAddr uint16
	ROBIdx  uint8
	LDWIdx  uint8
	STQIdx  uint8
	RXQIdx  uint8

	PhyDst  uint8
	PhyRS1  uint8
	PhyRS2  uint8
	PhyRS3  uint8
	PhyPred uint8

	PhyRS1Busy  bool
	PhyRS2Busy  bool
	PhyRS3Busy  bool
	PhyPredBusy bool
	StalePhyDst uint8

	Xcpt        bool
	XcptCause   XcptCause
	Bypass      bool
	MemCmd      MemCmd
	MemSz       Width
	MemSigned   bool
	IsFence     bool
	IsFencei    bool
	IsAMO       bool
	UsesLDQ     bool
	UsesSTQ     bool
	IsSysPC2EPC bool
	IsUnique    bool

	FlushOnCommit bool

	IsSFBBranch bool
	IsSFBShadow bool
	LogDstIsRS1 bool

	LogDst uint8
	LogRS1 uint8
	LogRS2 uint8
	LogRS3 uint8

	IsDst       bool
	DstRtype    RegType
	LogRS1RType RegType
	LogRS2RType RegType
	FRS3        bool

	FPVal    bool
	FPSingle bool

	XcptPgFlt      bool
	XcptICache     bool
	XcptMisaligned bool
	BreakDebug     bool
	BreakXcpt      bool

	DebugFsrc uint8
	DebugTsrc uint8

	AllocateBranchTag bool
	RFWen             bool
	Unsafe            bool
}

Uop contains the information passed through the pipeline for every operation.

type Width

type Width uint8

const (
	Byte Width = iota
	Half
	Word
	Double
	Quad
)

type XcptCause

type XcptCause uint16

const (
	NoCause XcptCause = iota
	DebugTriggerCause
	BreakCause
	FetchPgFaultCause
	FetchAccessCause
	IllInsnCause
)