Documentation
¶
Index ¶
- Constants
- Variables
- type Device
- func (d *Device) Configure() error
- func (d *Device) ConfigureMultisynth(output uint8, pll uint8, div uint32, num uint32, denom uint32) error
- func (d *Device) ConfigurePLL(pll uint8, mult uint8, num uint32, denom uint32) error
- func (d *Device) ConfigureRdiv(output uint8, div uint8) error
- func (d *Device) Connected() (bool, error)
- func (d *Device) DisableOutputs() error
- func (d *Device) DisableSpreadSpectrum() error
- func (d *Device) EnableOutputs() error
- func (d *Device) EnableSpreadSpectrum() error
- func (d *Device) GetFreqStep(pll uint8) uint64
- func (d *Device) OutputEnable(output uint8, enable bool) error
- func (d *Device) SetFrequency(freq uint64, output uint8, pll uint8) error
Constants ¶
const ( OUTPUT_ENABLE_CONTROL = 3 CLK0_CONTROL = 16 CLK1_CONTROL = 17 CLK2_CONTROL = 18 CLK3_CONTROL = 19 CLK4_CONTROL = 20 CLK5_CONTROL = 21 CLK6_CONTROL = 22 CLK7_CONTROL = 23 MULTISYNTH0_PARAMETERS_1 = 42 MULTISYNTH0_PARAMETERS_3 = 44 MULTISYNTH1_PARAMETERS_1 = 50 MULTISYNTH1_PARAMETERS_3 = 52 MULTISYNTH2_PARAMETERS_1 = 58 MULTISYNTH2_PARAMETERS_3 = 60 SPREAD_SPECTRUM_PARAMETERS = 149 PLL_RESET = 177 CRYSTAL_INTERNAL_LOAD_CAPACITANCE = 183 )
const ( CRYSTAL_LOAD_6PF = (1 << 6) CRYSTAL_LOAD_8PF = (2 << 6) CRYSTAL_LOAD_10PF = (3 << 6) )
const ( CRYSTAL_FREQ_25MHZ = 25000000 CRYSTAL_FREQ_27MHZ = 27000000 )
const ( PLL_A = iota PLL_B )
const ( R_DIV_1 = iota R_DIV_2 R_DIV_4 R_DIV_8 R_DIV_16 R_DIV_32 R_DIV_64 R_DIV_128 )
const ( MULTISYNTH_DIV_4 = 4 MULTISYNTH_DIV_6 = 6 MULTISYNTH_DIV_8 = 8 )
const ( CLKOUT_MIN_FREQ = 8000 // 8 kHz CLKOUT_MAX_FREQ = 150000000 // 150 MHz MULTISYNTH_MAX_FREQ = 150000000 // 150 MHz MULTISYNTH_SHARE_MAX = 100000000 // 100 MHz MULTISYNTH_DIVBY4_FREQ = 150000000 // 150 MHz PLL_VCO_MIN = 600000000 // 600 MHz PLL_VCO_MAX = 900000000 // 900 MHz )
Frequency constants (in Hz)
const AddressAlternative = 0x61 // Assumes ADDR pin is high
const AddressDefault = 0x60 // Assumes ADDR pin is low
The I2C address which this device listens to.
const (
SI5351_PLL_C_MAX = 1048575
)
Variables ¶
var ErrClockConflict = errors.New("Si5351 clock conflict with existing configuration")
var ErrFrequencyOutOfRange = errors.New("Si5351 frequency out of range")
var ErrInvalidParameter = errors.New("Si5351 invalid parameter")
var ErrNotInitialised = errors.New("Si5351 not initialised")
Functions ¶
This section is empty.
Types ¶
type Device ¶
type Device struct {
Address uint8
// contains filtered or unexported fields
}
Device wraps an I2C connection to a SI5351 device.
func New ¶
New creates a new SI5351 connection. The I2C bus must already be configured.
This function only creates the Device object, it does not touch the device.
func (*Device) ConfigureMultisynth ¶
func (d *Device) ConfigureMultisynth(output uint8, pll uint8, div uint32, num uint32, denom uint32) error
ConfigureMultisynth divider, which determines the output clock frequency based on the specified PLL input.
output The output channel to use (0..2)
pll The PLL input source to use, which must be one of:
- PLL_A
- PLL_B
div The integer divider for the Multisynth output.
If pure integer values are used, this value must be one of: - MULTISYNTH_DIV_4 - MULTISYNTH_DIV_6 - MULTISYNTH_DIV_8 If fractional output is used, this value must be between 8 and 900.
num The 20-bit numerator for fractional output (0..1,048,575).
Set this to '0' for integer output.
denom The 20-bit denominator for fractional output (1..1,048,575).
Set this to '1' or higher to avoid divide by zero errors.
Output Clock Configuration ¶
The multisynth dividers are applied to the specified PLL output, and are used to reduce the PLL output to a valid range (500kHz to 160MHz). The relationship can be seen in this formula, where fVCO is the PLL output frequency and MSx is the multisynth divider:
fOUT = fVCO / MSx
Valid multisynth dividers are 4, 6, or 8 when using integers, or any fractional values between 8 + 1/1,048,575 and 900 + 0/1 The following formula is used for the fractional mode divider:
a + b / c
a = The integer value, which must be 4, 6 or 8 in integer mode (MSx_INT=1) or 8..900 in fractional mode (MSx_INT=0). b = The fractional numerator (0..1,048,575) c = The fractional denominator (1..1,048,575)
NOTE: Try to use integers whenever possible to avoid clock jitter NOTE: For output frequencies > 150MHz, you must set the divider
to 4 and adjust to PLL to generate the frequency (for example a PLL of 640 to generate a 160MHz output clock). This is not yet supported in the driver, which limits frequencies to 500kHz .. 150MHz.
NOTE: For frequencies below 500kHz (down to 8kHz) Rx_DIV must be
used, but this isn't currently implemented in the driver.
func (*Device) ConfigurePLL ¶
ConfigurePLL sets the multiplier for the specified PLL pll The PLL to configure, which must be one of the following: - PLL_A - PLL_B
mult The PLL integer multiplier (must be between 15 and 90)
num The 20-bit numerator for fractional output (0..1,048,575). Set this to '0' for integer output.
denom The 20-bit denominator for fractional output (1..1,048,575). Set this to '1' or higher to avoid divider by zero errors.
PLL Configuration fVCO is the PLL output, and must be between 600..900MHz, where:
fVCO = fXTAL * (a+(b/c))
fXTAL = the crystal input frequency a = an integer between 15 and 90 b = the fractional numerator (0..1,048,575) c = the fractional denominator (1..1,048,575)
NOTE: Try to use integers whenever possible to avoid clock jitter (only use the a part, setting b to '0' and c to '1').
See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
func (*Device) DisableOutputs ¶
func (*Device) DisableSpreadSpectrum ¶
func (*Device) EnableOutputs ¶
func (*Device) EnableSpreadSpectrum ¶
EnableSpreadSpectrum enables spread spectrum modulation to reduce EMI.
func (*Device) GetFreqStep ¶
GetFreqStep returns the frequency step size of the radio in Hz. This is the smallest frequency increment that can be achieved, determined by the PLL frequency and denominator resolution. If pll is PLL_A, uses PLLA settings; if PLL_B, uses PLLB settings. Returns 0 if the specified PLL is not configured.
func (*Device) SetFrequency ¶
SetFrequency sets the clock frequency of the specified CLK output. Frequency range is 8 kHz to 150 MHz.
freq - Output frequency in Hz output - Clock output (0, 1, or 2 for this driver) pll - The PLL to use (PLL_A or PLL_B)
Source Files